Renesas SH7781 用户手册
7. Memory Management Unit (MMU)
Rev.1.00 Jan. 10, 2008 Page 153 of 1658
REJ09B0261-0100
Register Name
Abbreviation
Power-on
Reset
Reset
Manual
Reset
Reset
Sleep
Standby
Instruction re-fetch inhibit control
register
register
IRMCR
H'0000 0000 H'0000 0000 Retained
Retained
7.2.1
Page Table Entry High Register (PTEH)
PTEH consists of the virtual page number (VPN) and address space identifier (ASID). When an
MMU exception or address error exception occurs, the VPN of the virtual address at which the
exception occurred is set in the VPN bit by hardware. VPN varies according to the page size, but
the VPN set by hardware when an exception occurs consists of the upper 22 bits of the virtual
address which caused the exception. VPN setting can also be carried out by software. The number
of the currently executing process is set in the ASID bit by software. ASID is not updated by
hardware. VPN and ASID are recorded in the UTLB by means of the LDTLB instruction.
MMU exception or address error exception occurs, the VPN of the virtual address at which the
exception occurred is set in the VPN bit by hardware. VPN varies according to the page size, but
the VPN set by hardware when an exception occurs consists of the upper 22 bits of the virtual
address which caused the exception. VPN setting can also be carried out by software. The number
of the currently executing process is set in the ASID bit by software. ASID is not updated by
hardware. VPN and ASID are recorded in the UTLB by means of the LDTLB instruction.
After the ASID field in PTEH has been updated, execute one of the following three methods
before an access (including an instruction fetch) to the P0, P3, or U0 area that uses the updated
ASID value is performed.
before an access (including an instruction fetch) to the P0, P3, or U0 area that uses the updated
ASID value is performed.
1. Execute a branch using the RTE instruction. In this case, the branch destination may be the P0,
P3, or U0 area.
2. Execute the ICBI instruction for any address (including non-cacheable area).
3. If the R2 bit in IRMCR is 0 (initial value) before updating the ASID field, the specific
instruction does not need to be executed. However, note that the CPU processing performance
will be lowered because the instruction fetch is performed again for the next instruction after
the ASID field has been updated.
will be lowered because the instruction fetch is performed again for the next instruction after
the ASID field has been updated.
Note that the method 3 may not be guaranteed in the future SuperH Series. Therefore, it is
recommended that the method 1 or 2 should be used for being compatible with the future SuperH
Series.
recommended that the method 1 or 2 should be used for being compatible with the future SuperH
Series.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ASID
VPN
VPN
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W