Renesas SH7781 用户手册

7.   Memory Management Unit (MMU) 

Rev.1.00  Jan. 10, 2008  Page 177 of 1658 

REJ09B0261-0100 

 

This LSI supports the following MMU functions. 

1.  The MMU decodes the virtual address to be accessed by software, and performs address 

translation by controlling the UTLB/ITLB in accordance with the MMUCR settings. 

2.  The MMU determines the cache access status on the basis of the page management 

information read during address translation (C and WT bits). 

3.  If address translation cannot be performed normally in a data access or instruction access, the 

MMU notifies software by means of an MMU exception. 

4.  If address translation information is not recorded in the ITLB in an instruction access, the 

MMU searches the UTLB. If the necessary address translation information is recorded in the 
UTLB, the MMU copies this information into the ITLB in accordance with the LRUI bit 
setting in MMUCR. 

 

Software processing for the MMU consists of the following: 

1.  Setting of MMU-related registers. Some registers are also partially updated by hardware 

automatically. 

2.  Recording, deletion, and reading of TLB entries. There are two methods of recording UTLB 

entries: by using the LDTLB instruction, or by writing directly to the memory-mapped UTLB. 
ITLB entries can only be recorded by writing directly to the memory-mapped ITLB. Deleting 
or reading UTLB/ITLB entries is enabled by accessing the memory-mapped UTLB/ITLB. 

3.  MMU exception handling. When an MMU exception occurs, processing is performed based on 

information set by hardware.