Renesas SH7781 用户手册
7. Memory Management Unit (MMU)
Rev.1.00 Jan. 10, 2008 Page 184 of 1658
REJ09B0261-0100
REJ09B0261-0100
3. In TLB compatible mode, execute the LDTLB instruction and write the contents of PTEH and
PTEL to the TLB.
In TLB extended mode, execute the LDTLB instruction and write the contents of PTEH,
PTEL, PTEA to the UTLB.
In TLB extended mode, execute the LDTLB instruction and write the contents of PTEH,
PTEL, PTEA to the UTLB.
4. Finally, execute the exception handling return instruction (RTE) to terminate the exception
handling routine and return control to the normal flow. The RTE instruction should be issued
at least one instruction after the LDTLB instruction.
at least one instruction after the LDTLB instruction.
For the execution of the LDTLB instruction, see section 7.10.1, Note on Using LDTLB
Instruction.
Instruction.
7.6.3
Instruction TLB Protection Violation Exception
An instruction TLB protection violation exception occurs when, even though an ITLB entry
contains address translation information matching the virtual address to which an instruction
access is made, the actual access type is not permitted by the access right specified by the PR or
EPR bit. The instruction TLB protection violation exception processing carried out by hardware
and software is shown below.
contains address translation information matching the virtual address to which an instruction
access is made, the actual access type is not permitted by the access right specified by the PR or
EPR bit. The instruction TLB protection violation exception processing carried out by hardware
and software is shown below.
(1)
Hardware Processing
In the event of an instruction TLB protection violation exception, hardware carries out the
following processing:
following processing:
1. Sets the VPN of the virtual address at which the exception occurred in PTEH.
2. Sets the virtual address at which the exception occurred in TEA.
3. Sets exception code H'0A0 in EXPEVT.
4. Sets the PC value indicating the address of the instruction at which the exception occurred in
SPC. If the exception occurred at a delay slot, sets the PC value indicating the address of the
delayed branch instruction in SPC.
delayed branch instruction in SPC.
5. Sets the SR contents at the time of the exception in SSR. The R15 contents at this time are
saved in SGR.
6. Sets the MD bit in SR to 1, and switches to privileged mode.
7. Sets the BL bit in SR to 1, and masks subsequent exception requests.
8. Sets the RB bit in SR to 1.
9. Branches to the address obtained by adding offset H'0000 0100 to the contents of VBR, and
starts the instruction TLB protection violation exception handling routine.