Renesas SH7781 用户手册

7.   Memory Management Unit (MMU) 

Rev.1.00  Jan. 10, 2008  Page 191 of 1658 

REJ09B0261-0100 

 

The ITLB address array is allocated to addresses H'F200 0000 to H'F2FF FFFF in the P4 area. An 
address array access requires a 32-bit address field specification (when reading or writing) and a 
32-bit data field specification (when writing). Information for selecting the entry to be accessed is 
specified in the address field, and VPN, V, and ASID to be written to the address array are 
specified in the data field. 

In the address field, bits [31:24] have the value H'F2 indicating the ITLB address array and the 
entry is specified by bits [9:8]. As only longword access is used, 0 should be specified for address 
field bits [1:0]. 

In the data field, bits [31:10] indicate VPN, bit [8] indicates V, and bits [7:0] indicate ASID. 

The following two kinds of operation can be used on the ITLB address array: 

1.  ITLB address array read 

VPN, V, and ASID are read into the data field from the ITLB entry corresponding to the entry 
set in the address field. 

2.  ITLB address array write 

VPN, V, and ASID specified in the data field are written to the ITLB entry corresponding to 
the entry set in the address field. 

 

Address field

31

23

0

1 1 1 1 0 0

0 0

1 0

E

Data field

31

10 9

0

V

VPN

VPN:

V:

 E:

*:

24

Virtual page number
Validity bit
Entry
Don't care 

10 9 8 7

2 1

9 8 7

ASID

ASID:

:

Address space identifier
Reserved bits (write value should be 0, 
and read value is undefined )

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