Renesas SH7781 用户手册

7.   Memory Management Unit (MMU) 

Rev.1.00  Jan. 10, 2008  Page 199 of 1658 

REJ09B0261-0100 

 

Setting the SE bit in PASCR to 1 changes mode from 29-bit address mode which handles the 29-
bit physical address space to 32-bit address extended mode which handles the 32-bit physical 
address space. 

P1 (0.5 Gbyte)

P1/P2

(1 Gbyte)

0.5 Gbyte

4 Gbytes

U0/P0

(2 Gbytes)

U0/P0

(2 Gbytes)

P2 (0.5 Gbyte)

P3 (0.5 Gbyte)

P3 (0.5 Gbyte)

P4 (0.5 Gbyte)

P4 (0.5 Gbyte)

Virtual address space

29-bits

address space

Virtual address space

32-bit

 address space

29-bit Physical address space

 (Normal mode)

32-bit Physical address space

(Extended mode)

 

In 32-bit address extended mode, the privileged space mapping buffer (PMB) is introduced. The 
PMB maps virtual addresses in the P1 or P2 area which are not translated in 29-bit address mode 
to the 32-bit physical address space. In areas which are target for address translation of the TLB 
(UTLB/ITLB), upper three bits in the PPN field of the UTLB or ITLB are extended and then 
addresses after the TLB translation can handle the 32-bit physical addresses. 

As for the cache operation, P1 area is cacheable and P2 area is non-cacheable in the case of 29-bit 
address mode, but the cache operation of both P1 and P2 area are determined by the C bit and WT 
bit in the PMB in the case of 32-bit address mode.