Renesas SH7781 用户手册

7.   Memory Management Unit (MMU) 

Rev.1.00  Jan. 10, 2008  Page 202 of 1658 
REJ09B0261-0100 

 

•  WT: Write-through bit 

Specifies the cache write mode. 

0: Copy-back mode 

1: Write-through mode 

•  UB: Buffered write bit 

Specifies whether a buffered write is performed. 

0: Buffered write (Data access of subsequent processing proceeds without waiting for the write 

to complete.) 

1: Unbuffered write (Data access of subsequent processing is stalled until the write has 

completed.) 

 

This LSI supports the following PMB functions. 

1.  Only memory-mapped write can be used for writing to the PMB. The LDTLB instruction 

cannot be used to write to the PMB. 

2.  Software must ensure that every accessed P1 or P2 address has a corresponding PMB entry 

before the access occurs. When an access to an address in the P1 or P2 area which is not 
recorded in the PMB is made, this LSI is reset by the TLB. In this case, the accessed address in 
the P1 or P2 area which causes the TLB reset is stored in the TEA and code H

′140 in the 

EXPEVT. 

3.  The SH-4A does not guarantee the operation when multiple hit occurs in the PMB. Special 

care should be taken when the PMB mapping information is recorded by software. 

4.  The PMB does not have an associative write function. 

5.  Since there is no PR field in the PMB, read/write protection cannot be preformed. The address 

translation target of the PMB is the P1 or P2 address. In user mode access, an address error 
exception occurs. 

6.  Both entries from the UTLB and PMB are mixed and recorded in the ITLB by means of the 

hardware ITLB miss handling. However, these entries can be identified by checking whether 
VPN[31:30] is 10 or not. When an entry from the PMB is recorded in the ITLB, H

′00, 01, and 

1 are recorded in the ASID, PR, and SH fields which do not exist in the PMB, respectively.