Renesas SH7781 用户手册
8. Caches
Rev.1.00 Jan. 10, 2008 Page 228 of 1658
REJ09B0261-0100
REJ09B0261-0100
3. Cache hit
The LRU bits is updated to indicate the way is the latest one.
4. Cache miss
Data is read into the cache line on a way which selected using the LRU bits to replace from the
physical address space corresponding to the virtual address. Data reading is performed, using
the wraparound method, in order from the quad-word data (8 bytes) including the cache-
missed data. In the prefetch operation, the CPU doesn't wait the data arrived. While the one
cache line of data is being read, the CPU can execute the next processing. When reading of one
line of data is completed, the tag corresponding to the physical address is recorded in the
cache, and 1 is written to the V bit, the LRU bits is updated to indicate the way is the latest
one.
physical address space corresponding to the virtual address. Data reading is performed, using
the wraparound method, in order from the quad-word data (8 bytes) including the cache-
missed data. In the prefetch operation, the CPU doesn't wait the data arrived. While the one
cache line of data is being read, the CPU can execute the next processing. When reading of one
line of data is completed, the tag corresponding to the physical address is recorded in the
cache, and 1 is written to the V bit, the LRU bits is updated to indicate the way is the latest
one.
8.4.3
IC Two-Way Mode
When the IC2W bit in RAMCR is set to 1, IC two-way mode which only uses way 0 and way 1 in
the IC is entered. Thus, power consumption can be reduced. In this mode, only way 0 and way 1
are used even if a memory-mapped IC access is made.
the IC is entered. Thus, power consumption can be reduced. In this mode, only way 0 and way 1
are used even if a memory-mapped IC access is made.
The IC2W bit should be modified by a program in the P2 area. At that time, if the valid line has
already been recorded in the IC, 1 should be written to the ICI bit in CCR and all entries in the IC
should be invalid before modifying the IC2W bit.
already been recorded in the IC, 1 should be written to the ICI bit in CCR and all entries in the IC
should be invalid before modifying the IC2W bit.
8.4.4
Instruction Cache Way Prediction Operation
This LSI incorporates an instruction cache (IC) way prediction scheme to reduce power
consumption. This is achieved by activating only the data array that corresponds to a predicted
way. When way prediction misses occur, data must be re-read from the right way, which may lead
to lower performance in instruction fetching. Setting the ICWPD bit to 1 disables the IC way
prediction scheme. Since way prediction misses do not occur in this mode, there is no loss of
performance in instruction fetching but the IC consumes more power. The ICWPD bit should be
modified by a program in the non-cacheable P2 area. If a valid line has already been recorded in
the IC at this time, invalidate all entries in the IC by writing 1 to the ICI bit in CCR before
modifying the ICWPD bit.
consumption. This is achieved by activating only the data array that corresponds to a predicted
way. When way prediction misses occur, data must be re-read from the right way, which may lead
to lower performance in instruction fetching. Setting the ICWPD bit to 1 disables the IC way
prediction scheme. Since way prediction misses do not occur in this mode, there is no loss of
performance in instruction fetching but the IC consumes more power. The ICWPD bit should be
modified by a program in the non-cacheable P2 area. If a valid line has already been recorded in
the IC at this time, invalidate all entries in the IC by writing 1 to the ICI bit in CCR before
modifying the ICWPD bit.