Renesas SH7781 用户手册
8. Caches
Rev.1.00 Jan. 10, 2008 Page 237 of 1658
REJ09B0261-0100
Address field
31
23
5 4 3 2 1 0
1 1 1 1 0 1 0 1
Entry
Data field
31
0
Longword data
24
1312
14
15
L
*
: Longword specification bits
: Don't care
: Don't care
Way
0
L
0
* * * * * * * * *
Figure 8.8 Memory-Mapped OC Data Array (Cache size = 32 Kbytes)
8.6.5
Memory-Mapped Cache Associative Write Operation
Associative writing to the IC and OC address arrays may not be supported in future SuperH-
family products. The use of instructions ICBI, OCBI, OCBP, and OCBWB is recommended.
These instructions handle ITLB misses, and notify instruction TLB miss exceptions and data TLB
miss exceptions, thus providing a sure way of controlling the IC and OC. As a transitional
measure, this LSI generates address errors when this function is used. If compatibility with
previous products is a crucial consideration, on the other hand, the MMCAW bit in EXPMASK
(H'FF2F 0004) can be set to 1 to enable this function. However, instructions ICBI, OCBI, OCBP,
and OCBWB should be used to guarantee compatibility with future SuperH-family products.
family products. The use of instructions ICBI, OCBI, OCBP, and OCBWB is recommended.
These instructions handle ITLB misses, and notify instruction TLB miss exceptions and data TLB
miss exceptions, thus providing a sure way of controlling the IC and OC. As a transitional
measure, this LSI generates address errors when this function is used. If compatibility with
previous products is a crucial consideration, on the other hand, the MMCAW bit in EXPMASK
(H'FF2F 0004) can be set to 1 to enable this function. However, instructions ICBI, OCBI, OCBP,
and OCBWB should be used to guarantee compatibility with future SuperH-family products.