Renesas SH7781 用户手册
9. On-Chip Memory
Rev.1.00 Jan. 10, 2008 Page 257 of 1658
REJ09B0261-0100
(3)
U Memory
Operand access from the CPU and read access from the FPU are performed via the read buffer.
The read buffer is configured with two sets of one-line 32-byte buffers, and holds up to two lines
which have been accessed through operand access by the CPU and accessed through read access
by the FPU. The U memory can be accessed in one cycle when the read buffer is hit. If the read
buffer is missed, 32-byte data including data required from the U memory is read out, and returned
to the CPU, and the read buffer is updated. Access in this case takes more than one cycle. The
LRU algorithm is used to determine which of the two read buffers to update. In write access, the U
memory is directly updated, and if the corresponding line is held in the read buffer, the read buffer
is invalidated. It is unnecessary to guarantee the coherency by software since the hardware
invalidates the read buffer even when the SuperHyway bus master module, such as DMAC,
rewrites the U memory.
The read buffer is configured with two sets of one-line 32-byte buffers, and holds up to two lines
which have been accessed through operand access by the CPU and accessed through read access
by the FPU. The U memory can be accessed in one cycle when the read buffer is hit. If the read
buffer is missed, 32-byte data including data required from the U memory is read out, and returned
to the CPU, and the read buffer is updated. Access in this case takes more than one cycle. The
LRU algorithm is used to determine which of the two read buffers to update. In write access, the U
memory is directly updated, and if the corresponding line is held in the read buffer, the read buffer
is invalidated. It is unnecessary to guarantee the coherency by software since the hardware
invalidates the read buffer even when the SuperHyway bus master module, such as DMAC,
rewrites the U memory.
9.3.3
Access from the SuperHyway Bus Master Module
On-chip memory is always accessed by the SuperHyway bus master module, such as DMAC, via
the SuperHyway bus which is a physical address bus. The same addresses as for the virtual
addresses must be used.
the SuperHyway bus which is a physical address bus. The same addresses as for the virtual
addresses must be used.
9.3.4
OL Memory Block Transfer
High-speed data transfer can be performed through block transfer between the OL memory and
external memory without cache utilization.
external memory without cache utilization.
Data can be transferred from the external memory to the OL memory through a prefetch
instruction (PREF). Block transfer from the external memory to the OL memory begins when the
PREF instruction is issued to the address in the OL memory area in the virtual address space.
instruction (PREF). Block transfer from the external memory to the OL memory begins when the
PREF instruction is issued to the address in the OL memory area in the virtual address space.
Data can be transferred from the OL memory to the external memory through a write-back
instruction (OCBWB). Block transfer from the OL memory to the external memory begins when
the OCBWB instruction is issued to the address in the OL memory area in the virtual address
space.
instruction (OCBWB). Block transfer from the OL memory to the external memory begins when
the OCBWB instruction is issued to the address in the OL memory area in the virtual address
space.
In either case, transfer rate is fixed to 32 bytes. Since the start address is always limited to a 32-
byte boundary, the lower five bits of the address indicated by Rn are ignored, and are always dealt
with as all 0s. In either case, other pages and cache can be accessed during block transfer, but the
CPU will stall if the page which is being transferred is accessed before data transfer ends.
byte boundary, the lower five bits of the address indicated by Rn are ignored, and are always dealt
with as all 0s. In either case, other pages and cache can be accessed during block transfer, but the
CPU will stall if the page which is being transferred is accessed before data transfer ends.
The physical addresses [28:0] of the external memory performing data transfers with the OL
memory are specified as follows according to whether the MMU is enabled or disabled.
memory are specified as follows according to whether the MMU is enabled or disabled.