Renesas SH7781 用户手册

10.   Interrupt Controller (INTC) 

Rev.1.00  Jan. 10, 2008  Page 272 of 1658 
REJ09B0261-0100 

 

Table 10.2 shows the pin configuration. 

NMI Nonmaskable 

interrupt  
input pin 

Input 

Nonmaskable interrupt request signal input 

IRQ/

IRL7 to 

IRQ/

IRL0 

External 
interrupt  
input pins 

Input 

Interrupt request signal input of IRQ7 to IRQ0 or 

IRL[7:4] 

and 

IRL[3:0] 

The IRQ/

IRL7 pin is multiplexed with FD7 (FLCTL I/O), 

MODE3 (mode control input), and port L1 (GPIO I/O) pin,  
the IRQ/

IRL6 pin is multiplexed with FD6 (FLCTL I/O), 

MODE2 (mode control input), and port L2 (GPIO I/O) pin, 
the IRQ/

IRL5 pin is multiplexed with FD5 (FLCTL I/O), 

MODE1 (mode control input), and port L3 (GPIO I/O) pin, 
and the IRQ/

IRL4 pin is multiplexed with FD4 (FLCTL I/O), 

MODE3 (mode control input), and port L4 (GPIO I/O) pin. 

IRQOUT Interrupt 

request  
output pin 

Output  Informs an external device of the generation of an interrupt 

request. 

The 

IRQOUT pin is multiplexed with MRESETOUT (reset, 

watchdog timer (WDT) output pin). 
IRQOUT outputs the low level even if the interrupt request is 
not accepted by the CPU because of the priority of a 
generated interrupt request being lower than SR.IMASK. 
However, 

IRQOUT is not asserted in the following cases: 

(1) IRL interrupt 

•  The IRL interrupt is masked by INTMASK1, or 
•  The 

IRQ interrupt is masked by INTMASK2. 

(2) 

IRQ interrupt  

•  The interrupt is masked by INTMASK1, or 
•  The priority of the IRQ interrupt is set to H'0 by INTPRI 
(3) On-chip module interrupt 

•  The on-chip module interrupt is masked by INT2MSKR, 

or 

•  The priority is set to H'00 or H'01 by INT2PRI0 to 

INT2PRI9.