Renesas SH7781 用户手册
10. Interrupt Controller (INTC)
Rev.1.00 Jan. 10, 2008 Page 300 of 1658
REJ09B0261-0100
REJ09B0261-0100
3. Branch to the device driver.
4. In the device driver operating in user mode, set the UIMASK bits to mask the B-type
interrupts.
5. Process more urgent interrupts in the device driver.
6. Clear the UIMASK bit to 0 and return from the processing by the device driver.
10.3.3
On-chip Module Interrupt Priority Registers
(1)
Interrupt Priority Registers (INT2PRI0 to INT2PRI9)
INT2PRI0 to INT2PRI9 are 32-bit readable/writable registers that set priority levels (31 to 0) of
the on-chip peripheral module interrupts. These registers are initialized to H'0000 0000 by a reset.
the on-chip peripheral module interrupts. These registers are initialized to H'0000 0000 by a reset.
These registers can set the priority of each interrupt source in 30 levels (H'00 and H'01 mask the
interrupt request) by the 5-bit field.
interrupt request) by the 5-bit field.
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
30
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
⎯
⎯
⎯
⎯
⎯
⎯
R/W
R/W
R/W
R/W
R/W
R
R
R
R/W
R/W
R/W
R/W
R/W
R
R
R
Bit:
Initial value:
R/W:
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
⎯
⎯
⎯
⎯
⎯
⎯
R/W
R/W
R/W
R/W
R/W
R
R
R
R/W
R/W
R/W
R/W
R/W
R
R
R
Bit:
Initial value:
R/W:
Table 10.5 shows the correspondence between interrupt request sources and bits in INT2PRI0 to
INT2PRI9.
INT2PRI9.