Renesas SH7781 用户手册

10.   Interrupt Controller (INTC) 

Rev.1.00  Jan. 10, 2008  Page 345 of 1658 

REJ09B0261-0100 

 

To clear the interrupt request retained in the INTC, follow the procedure below. 

⎯  Clearing IRQ interrupt requests at edge detection 

To clear the interrupt requests IRQ7 to IRQ0 setting edge detection, read the IR7 to IR0 
bits corresponding to INTREQ as 1 and write 0 to the bits. The IRQ interrupt request 
being detected cannot be cleared even if 1 is written to the corresponding bit in 
INTMSK0. 

 

= 0 

⎯  Clearing IRL interrupt requests 

To clear the IRL interrupt requests from the IRQ/

IRL[3:0] pins, write 1 to the IM10 bit 

in INTMSK1. To clear the IRL interrupt requests from the IRQ/

IRL[7:4] pins, write 1 to 

the IM11 bit in INTMSK1. The IRL interrupt request being detected cannot be cleared 
even if masking is performed on INTMSK2 by the level. 

 

⎯  Clearing IRQ interrupt requests at level detection 

To clear the IRQ7 to IRQ0 interrupt request setting level detection, write 1 to the 
corresponding IM07 to IM00 bits in INTMSK0. The IRQ interrupt request being 
detected cannot be cleared even if 0 is written to the corresponding bit in INTPRI. The 
IRQ interrupt request being detected can be checked by reading from INTREQ. 

 

= 1 

The INTC does not retain the interrupt source even if IRQ interrupts are detected at level detection 
or IRL interrupt requests are detected.