Renesas SH7781 用户手册

11.   Local Bus State Controller (LBSC) 

Rev.1.00  Jan. 10, 2008  Page 350 of 1658 
REJ09B0261-0100 

 

Table 11.1 shows the LBSC pin configuration. 

A25 to A0 

Address Bus 

O 

Address output 

D63 to D0 

Data Bus 

I/O Data 

input/output 

These pins are multiplexed as follows: 

D63 to D56: PCI, DU and ports A7 to A0 (GPIO 

input/output) 

D55 to D48: PCI, DU and ports B7 to B0 (GPIO 

input/output) 

D47 to D40: PCI, DU and ports C7 to C0 (GPIO 

input/output) 

D39 to D32: PCI, DU and ports D7 to D0 (GPIO 

input/output) 

D31 to D24: ports F7 to F0 (GPIO input/output) 

D23 to D16: ports G7 to G0 (GPIO input/output) 

BS 

Bus Cycle Start  O 

Signal that indicates the start of a bus cycle 

Asserted once for a burst transfer when the MPX 
interface is set 

Asserted in every data cycle in other burst 
transfers 

CS6 to CS0 

Chip Select 6 to 
0 

O 

Chip select signals that indicates the area being 
accessed. 

CS5 and CS6 can also be used as 

CE1A and CE1B of the PCMCIA respectively. 

R/

W 

Read/Write 

O 

Data bus input/output direction designation 
signal. Also used as the PCMCIA interface write 
designation signal 

RD/FRAME Read/Cycle 

Frame 

O 

Strobe signal indicating a read cycle. 

Used for 

FRAME signal when the MPX bus is 

used