Renesas SH7781 用户手册

11.   Local Bus State Controller (LBSC) 

Rev.1.00  Jan. 10, 2008  Page 403 of 1658 

REJ09B0261-0100 

 

The strobe signals for the SRAM interface in this LSI are output primarily based on the SRAM 
connection. Figure 11.5 shows the basic timing of the SRAM interface. Normal access without 
wait cycles is completed in two cycles. The 

BS signal is asserted for one or two cycles to indicate 

the start of a bus cycle. The 

CSn signal is asserted at the rising edge of the clock in the T1 state, 

and negated at the next rising edge of the clock in the T2 state. Therefore, there is no negation 
period in accesses at minimum pitch. 

In reading, an access size is not specified. The output of an access address on the address pins 
(A25 to A0) is correct, however, since the access size is not specified, 32-bit data is always output 
when a 32-bit device is in use, and 16-bit data is output when a 16-bit device is in use. During 
writing, only the 

WE signal corresponding to the byte to be written is asserted. For details, see 

section 11.5.1, Endian/Access Size and Data Alignment. 

In 32-byte transfer, a total of 32 bytes are transferred continuously according to the bus width set. 
The first access is performed on the data for which an access request is issued, and the remaining 
accesses are performed in wraparound method according to the set bus width. The bus is not 
released during this transfer.