Renesas SH7781 用户手册

11.   Local Bus State Controller (LBSC) 

Rev.1.00  Jan. 10, 2008  Page 427 of 1658 

REJ09B0261-0100 

 

When both the MODE 7 pin is set to 0 at a power-on reset by the 

PRESET pin, the MPX interface 

is selected for area 0. The MPX interface is selected for areas 1 to 6 by the MPX bit in CS1BCR, 
CS2BCR, and CS4BCR to CS6BCR. The MPX interface provides an address/data multiplex-type 
bus protocol and facilitates connection with external memory controller chips using an 
address/data multiplex-type 64- or 32-bit single bus. A bus cycle consists of an address phase and 
a data phase. In the address phase, address information is output on D25 to D0, and the access size 
is output on D63 to D61 for the 64-bit bus and on D31 to D29 for the 32-bit bus. The 

BS signal is 

asserted for one cycle to indicate the address phase. The 

CSn signal is asserted at the rising edge in 

Tm1 and is negated after the end of the last data transfer in the data phase. Therefore, a negation 
cycle is not generated in the case of minimum pitch access. The 

FRAME signal is asserted at the 

rising edge in Tm1 and negated at the start of the last data transfer cycle in the data phase. 
Therefore, an external device for the MPX interface must internally store the address information 
and access size output in the address phase and perform data input/output for the data phase. For 
details, see section 11.5.1, Endian/Access Size and Data Alignment. 

Values output to address pins A25 to A0 are not guaranteed. 

In 32-byte transfer, a total of 32 bytes are transferred continuously according to the set bus width. 
The first access is performed on the data for which an access request is issued, and the remaining 
accesses are performed according to the set bus width. If the access size is larger than the bus 
width, a burst access with continuing multiple data cycles occurs after one address output. The bus 
is not released during this transfer. 

0  0 0 Byte 

  

1 

Word 

 

1 0 Longword 

  

1 

Unused 

1  X X 32-byte 

burst 

Legend: 

X: Don't care