Renesas SH7781 用户手册

12.   DDR2-SDRAM Interface (DBSC2) 

Rev.1.00  Jan. 10, 2008  Page 457 of 1658 

REJ09B0261-0100 

 

Section 12   DDR2-SDRAM Interface (DBSC2) 

The DDR2-SDRAM interface (DBSC2) controls the DDR2-SDRAM. 

•  Supports 32-bit and 16-bit external data bus widths 
•  Supports from DDR2-600 (controller operation at 300 MHz) to DDR2-400 (controller 

operation at 200 MHz) 

•  Connects to 64-bit SuperHyway internal bus 
•  Supports 1:1 clock ratio between SuperHyway clock and DDR clock 
•  Queue provided for interface with SuperHyway 
•  During power-on reset, pin MODE8 can be used to switch between big- and little-endian 
•  Supports 4-bank and 8-bank DDR2-SDRAMs 
•  Supports sequential mode with burst length 4 
•  Supports Additive Latency (AL) of 0 only 
•  Supports differential data strobe signal (DQS, DQS) 

Note: RDQS is not supported. 

•  Supports self-refresh 
•  Supports power supply backup mode 
•  Supported DDR2-SDRAM addresses × bit widths (total capacity) are as follows. 

For details, refer to tables 12.12 through 12.19. 

(When using 8-bank products, please refer to section 12.5.8, Important Information Regarding 
Use of 8-Bank DDR2-SDRAM Products.) 
⎯  DDR2-SDRAM data bus width: 32 bits 

•  Two 256 Mbits (16M × 16 bits) connected in parallel (total capacity = 512 Mbits) 
•  Four 256 Mbits (32M × 8 bits) connected in parallel (total capacity = 1 Gbit) 
•  Two 512 Mbits (32M × 16 bits) connected in parallel (total capacity = 1 Gbit) 
•  Four 512 Mbits (64M × 8 bits) connected in parallel (total capacity = 2 Gbits) 
•  Two 1 Gbit (64M × 16 bits) connected in parallel (total capacity = 2 Gbits) 
•  Four 1 Gbit (128M × 8 bits) connected in parallel (total capacity = 4 Gbits) 
•  Two 2 Gbits (128M × 16 bits) connected in parallel (total capacity = 4 Gbits) 
•  Four 2 Gbits (256M × 8 bits) connected in parallel (total capacity = 8 Gbits)