Renesas SH7781 用户手册
12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 483 of 1658
REJ09B0261-0100
12.4.2
SDRAM Operation Enable Register (DBEN)
The SDRAM operation enable register (DBEN) is a readable/writable register. It is initialized only
upon power-on reset.
upon power-on reset.
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
30
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
BIt:
Initial value:
R/W:
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ACEN
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
BIt:
Initial value:
R/W:
Bit Bit
Name
Initial
Value R/W
Value R/W
Description
31 to 1
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
guaranteed.
0
ACEN
0
R/W
SDRAM Access Enable Bit
By setting this bit, data accessing of SDRAM is enabled.
When set to 0, access is disabled; when set to 1,
access is enabled. When access is disabled, attempts
to access SDRAM are ignored. This bit is used for the
initialization sequence or self-refresh operation.
When set to 0, access is disabled; when set to 1,
access is enabled. When access is disabled, attempts
to access SDRAM are ignored. This bit is used for the
initialization sequence or self-refresh operation.
0: Disables access
1: Enables access