Renesas SH7781 用户手册
12. DDR2-SDRAM Interface (DBSC2)
Rev.1.00 Jan. 10, 2008 Page 507 of 1658
REJ09B0261-0100
12.4.13
DDRPAD DIC, ODT, OCD Setting Register (DBDICODTOCD)
The SDRAM refresh status register (DBRFSTS) is a readable/writable register. It is initialized
only upon power-on reset.
only upon power-on reset.
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
30
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DIC
DIC_CK
DIC_DQ
DIC_AD
⎯
⎯
⎯
⎯
DDRSIG
⎯
⎯
⎯
⎯
⎯
⎯
⎯
R/W
R/W
R/W
R/W
R
R
R
R
R/W
R
R
R
R
R
R
R
BIt:
Initial value:
R/W:
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
T_ODT0
T_ODT1
ODT_
EARLY
ODTEN0
ODTEN1
⎯
⎯
⎯
R/W
R/W
R/W
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R
R
R
BIt:
Initial value:
R/W:
Bit Bit
Name
Initial
Value R/W
Value R/W
Description
31 to 25
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
guaranteed.
24
DDRSIG
0
R/W
Write Preamble Time Setting Bit
Sets the preamble time of the DQS signal to be output
when data is written to the DDR2-SDRAM. The number
of cycles is the number of DDR clock cycles.
when data is written to the DDR2-SDRAM. The number
of cycles is the number of DDR clock cycles.
0: Write preamble time = 0.5 cycle
1: Write preamble time = 1 cycle
23 to 20
⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
guaranteed.
19
DIC_AD
0
R/W
Address and Command Pin Impedance Value
This bit should be set to the same value as the value set
for DIC of EMRS(1) in the DDR2-SDRAM.
for DIC of EMRS(1) in the DDR2-SDRAM.
0: Normal
1: Weak