Renesas SH7781 用户手册

12.   DDR2-SDRAM Interface (DBSC2) 

Rev.1.00  Jan. 10, 2008  Page 520 of 1658 
REJ09B0261-0100 

 

When the auto-refresh enable bit (ARFEN) in the SDRAM refresh control register 0 
(DBRFCNT0) is 1, the auto-refresh command is issued periodically. If accessing data in the 
SDRAM, always make sure this is set. 

The average refresh interval is set in the TREFI bits in the SDRAM refresh control register 1 
(DBRFCNT1).  

In order to minimize reductions in the data transfer capability caused by auto-refreshing, the 
timing at which auto-refreshing is carried out can be divided into three levels and controlled: 

•  Level 0: Refreshing is done in vacant periods between commands being received from the 

SuperHyway bus. 

•  Level 1: Refreshes are issued during request empty cycles.  
•  Level 2: Refreshing is not done. 

 

The threshold values for level 0 and level 1 are set using the LV0TH bit in the SDRAM refresh 
control register 2 (DBRFCNT2), and the threshold values for level 1 and level 2 are set using the 
LV1TH bit. 

The refresh timing is controlled using a 14-bit refresh counter. The refresh counter counts down 
based on the DDR clock, until a refresh is carried out. When a refresh is carried out, the counter 
value increments by the amount of the average refresh interval set with the TREFI bits in 
DBRFCNT1. Figure 12.7 shows an example of the refresh operation and the update of the refresh 
counter. 

If there is a bank that is open before the auto-refresh is carried out, the DBSC2 automatically uses 
the PALL (precharge all banks) command to precharge all of the banks, and then issues the REF 
(auto-refresh) command. Consequently, after the refresh takes place, data access for all of the 
banks will be in the missed page state.