Renesas SH7781 用户手册

12.   DDR2-SDRAM Interface (DBSC2) 

Rev.1.00  Jan. 10, 2008  Page 550 of 1658 
REJ09B0261-0100 

 

The MCKE signal operation is explained using figure 12.24. Here, the explanation assumes that 
MBKPRST is high-level input. Prior to power-on reset the MCKE signal is indefinite, but upon 
power-on reset is output at low level. After release of power-on reset, by writing 011 to the CMD 
bits in the SDRAM command control register (DBCMDCNT), the MCKE signal output is at high 
level, corresponding to the enable state. Once the MCKE signal is output at a high level in this 
way, the DBSC2 does not output a low-level MCKE signal except when causing a transition to 
self-refresh state. (Once the CMD bits in DBCMDCNT are set to 011, no matter what value is 
subsequently written to CMD, the MCKE signal is never output at low level.) After the transition 
to self-refresh state, when 0 is written to SRFEN in DBRFCNT0 to release the self-refresh state, 
the MCKE signal output returns to high level. 

MCKE

Undefined

Power-on reset

Power-on reset canceled

011 is written to the CMD2 to CMD0 bits 
in DBCMDCNT.

The SRFEN bit in DBRFCNT0 is set to 
1 (transition to self-refresh state).

The SRFEN bit in DBRFCNT0 is cleared to 
0 (release of self-refresh state).