Renesas SH7781 用户手册
13. PCI Controller (PCIC)
Rev.1.00 Jan. 10, 2008 Page 590 of 1658
REJ09B0261-0100
REJ09B0261-0100
13.3.3
PCI Local Registers
(1)
PCI Control Register (PCICR)
PCICR is a 32-bit register which controls the operation of the PCIC in this LSI.
Writing to this register is valid only when the value of bits 31 to 24 are H'A5.
R/W
R/W
R/W
R
R
R/W
R
R/W
R/W
R/W
R/W
R
R
R
R
SH R/W:
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
PCI R/W:
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
SH R/W:
PCI R/W:
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
30
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Bit:
Initial value:
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
0
0
0
x
x
0
0
0
0
0
0
0
0
0
0
RST
CTL
CFINT
IOCS
R
x
—
—
—
BMAM
—
TBS
PFE
FTO
PFCS
—
—
—
—
Bit:
Initial value:
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
31 to 24
⎯ H'00
SH:
R/W
PCI: R
Reserved
These bits should be set to H'A5 (write H'A5 to these
bits) only before bits 11 to 8, 6, and 2 to 0 are written.
bits) only before bits 11 to 8, 6, and 2 to 0 are written.
These bits are always read as 0.
23 to 12
⎯
All 0
SH: R
PCI: R
Reserved
These bits are always read as 0. The write value
should always be 0.
should always be 0.
11 PFCS
0 SH:
R/W
PCI: R
PCI Pre-Fetch Command Setting
Specifies the access size for pre-fetch when the target
memory read access is issued by an external PCI
device.
memory read access is issued by an external PCI
device.
This bit is valid only when the PFE bit is 1.
0: 8-byte pre-fetch is always performed
1: 32-byte pre-fetch is always performed