Renesas SH7781 用户手册
15. Clock Pulse Generator (CPG)
Rev.1.00 Jan. 10, 2008 Page 749 of 1658
REJ09B0261-0100
15.6
How to Change the Frequency
To change the frequency of the internal clock and the local bus clock (CLKOUT) with software,
set frequency control registers FRQCR0 and FRQCR1 according to the following procedure.
Tables 15.8 to 15.11 list the selectable combinations of frequencies.
set frequency control registers FRQCR0 and FRQCR1 according to the following procedure.
Tables 15.8 to 15.11 list the selectable combinations of frequencies.
15.6.1
Changing the Frequency of Clocks Other than the Bus Clock
When changing the frequency of a clock except the bus clock, disable counting-up by the WDT.
The following describes the procedure for changing the frequency.
1. In FRQCR1, set a value (other than H'0) in the bit corresponding to the clock for which you
want to change the division ratio.*
2. Set H'CF000001 in FRQCR0 to enable execution of the sequence that changes the frequency.
The sequence that changes the frequency starts.
3. When H'00000000 is read from FRQCR0, the sequence that changes the frequency has
finished. The internal clock has been changed to the clock with the specified division ratio.
Note: * When setting a value except H'0 in the MFC3 to MFC0 bits in FRQCR1 to change the
DDR clock frequency, switch SDRAM to the self-refreshing state before executing
step (2) above. For details on how to switch to or release the self-refreshing state, see
section 12, DDR2-SDRAM Interface (DBSC2).
step (2) above. For details on how to switch to or release the self-refreshing state, see
section 12, DDR2-SDRAM Interface (DBSC2).
15.6.2
Changing the Bus Clock Frequency
When changing the bus clock frequency, start counting-up by the WDT after the oscillation of
PLL circuit 2 is stable. When a WDT overflow occurs during counting, this LSI resumes
operation.
PLL circuit 2 is stable. When a WDT overflow occurs during counting, this LSI resumes
operation.
Figures 15.2 and 15.3 show the timing of the CLKOUT and CLKOUTENB pins when the bus
clock frequency is changed.
clock frequency is changed.
The following describes the procedure for changing the frequency.
1. Write 0 to the TME bit in WDTCSR to stop the WDT.
2. In WDTBST, after the oscillation of PLL circuit 2 is stable, set the time that can elapse before
the LSI resumes operation. Writing H'55000001 sets the minimum value. Writing H'55000000
sets the maximum value.
sets the maximum value.
3. In FRQCR1, set a value (except H'0) in the bit corresponding to the clock for which you want
to change the division ratio.*