Renesas SH7781 用户手册
16. Watchdog Timer and Reset (WDT)
Rev.1.00 Jan. 10, 2008 Page 772 of 1658
REJ09B0261-0100
REJ09B0261-0100
16.4.4
Time until WDT Counters Overflow
The relationship between WDTCNT and WDTBCNT is shown in figure 16.2. The example shown
in the figure is the operation in interval timer mode, where WDTCNT restarts counting after it has
overflowed. In watchdog timer mode, WDTCNT and WDTBCNT are cleared to 0 after the reset
state is exited and start counting up again.
in the figure is the operation in interval timer mode, where WDTCNT restarts counting after it has
overflowed. In watchdog timer mode, WDTCNT and WDTBCNT are cleared to 0 after the reset
state is exited and start counting up again.
WDTCNT value
WDTBCNT value
WDTST
H'0000 0000
H'0003 FFFF
H'0000 0000
Incremented every
peripheral clock (Pck)
cycle
peripheral clock (Pck)
cycle
Counting starts
Flag is set
Time
Time
TME
WOVF
IOVF
Incremented on each
WDTBCNT overflow
WDTBCNT overflow
Cleared to 0
on overflow
on overflow
Cleared to 0
on overflow
on overflow
Figure 16.2 WDT Counting Operations (Example in Interval Timer Mode)