Renesas SH7781 用户手册
18. Timer Unit (TMU)
Rev.1.00 Jan. 10, 2008 Page 804 of 1658
REJ09B0261-0100
REJ09B0261-0100
18.3.1
Timer Start Registers (TSTRn) (n = 0, 1)
The TSTR registers are 8-bit readable/writable registers that specifies whether TCNT of the
corresponding channel is operated or stopped.
corresponding channel is operated or stopped.
• TSTR0
0
1
2
3
4
5
6
7
0
0
0
0
0
0
0
0
STR0
STR1
STR2
—
—
—
—
—
R/W
R/W
R/W
R
R
R
R
R
BIt:
Initial value:
R/W:
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
7 to 3
—
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
always be 0.
2
STR2
0
R/W
Counter Start 2
Specifies whether TCNT2 is operated or stopped.
0: TCNT2 count operation is stopped
1: TCNT2 performs count operation
1
STR1
0
R/W
Counter Start 1
Specifies whether TCNT1 is operated or stopped.
0: TCNT1 count operation is stopped
1: TCNT1 performs count operation
0
STR0
0
R/W
Counter Start 0
Specifies whether TCNT0 is operated or stopped.
0: TCNT0 count operation is stopped
1: TCNT0 performs count operation