Renesas SH7781 用户手册
19. Display Unit (DU)
Rev.1.00 Jan. 10, 2008 Page 854 of 1658
REJ09B0261-0100
REJ09B0261-0100
Bit Bit
Name
Initial
Value R/W
Value R/W
Internal
Update Description
Update Description
9
RICL
Undefined W
None
Vertical Blanking Flag Clear
0: The RINT flag in DSSR is not changed.
1: The RINT flag in DSSR is cleared to 0.
8
HBCL
Undefined W
None
Vertical Blanking Flag Clear
0: The HBK flag in DSSR is not changed.
1: The HBK flag in DSSR is cleared to 0.
7 to 0
⎯ All
0
R
⎯ Reserved
These bits are always read as 0. The write value
should always be 0.
should always be 0.
19.3.5
Display Unit Interrupt Enable Register (DIER)
The display unit interrupt enable register (DIER) is a register which enables interrupts to the CPU
the causes of which are internal states of the display unit (DU) reflected in DSSR. When bits are
set in this register, if bits in the same bit positions in DSSR are set, an interrupt is issued to the
CPU.
the causes of which are internal states of the display unit (DU) reflected in DSSR. When bits are
set in this register, if bits in the same bit positions in DSSR are set, an interrupt is issued to the
CPU.
R/W:
Internal update:
R/W:
Internal update:
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
30
Bit:
Initial value:
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
R
R
R
R
R
R
R
R
R/W
R/W
R
R/W
R
R
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
HBE
RIE
—
VBE
—
—
TVE
FRE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
Bit:
Initial value: