Renesas SH7781 用户手册

 

Rev.1.00  Jan. 10, 2008  Page ix of xxx 

REJ09B0261-0100 

 

Contents 

Section 1   Overview

.................................................................................................................. 1

 

1.1

 

Features of the SH7785.......................................................................................................... 1

 

1.2

 

Block Diagram ..................................................................................................................... 13

 

1.3

 

Pin Arrangement Table ........................................................................................................ 14

 

1.4

 

Pin Arrangement .................................................................................................................. 22

 

1.5

 

Physical Memory Address Map ........................................................................................... 24

 

Section 2   Programming Model

........................................................................................... 25 

2.1

 

Data Formats........................................................................................................................ 25

 

2.2

 

Register Descriptions ........................................................................................................... 26

 

2.2.1

 

Privileged Mode and Banks .................................................................................. 26

 

2.2.2

 

General Registers.................................................................................................. 30

 

2.2.3

 

Floating-Point Registers ....................................................................................... 31

 

2.2.4

 

Control Registers .................................................................................................. 33

 

2.2.5

 

System Registers................................................................................................... 35

 

2.3

 

Memory-Mapped Registers.................................................................................................. 39

 

2.4

 

Data Formats in Registers .................................................................................................... 40

 

2.5

 

Data Formats in Memory ..................................................................................................... 40

 

2.6

 

Processing States.................................................................................................................. 41

 

2.7

 

Usage Notes ......................................................................................................................... 43

 

2.7.1

 

Notes on Self-Modifying Code............................................................................. 43

 

Section 3   Instruction Set

....................................................................................................... 45

 

3.1

 

Execution Environment ....................................................................................................... 45

 

3.2

 

Addressing Modes ............................................................................................................... 47

 

3.3

 

Instruction Set ...................................................................................................................... 52

 

Section 4   Pipelining

............................................................................................................... 65

 

4.1

 

Pipelines............................................................................................................................... 65

 

4.2

 

Parallel-Executability........................................................................................................... 76

 

4.3

 

Issue Rates and Execution Cycles........................................................................................ 79

 

Section 5   Exception Handling

............................................................................................ 89 

5.1

 

Summary of Exception Handling......................................................................................... 89

 

5.2

 

Register Descriptions ........................................................................................................... 89

 

5.2.1

 

TRAPA Exception Register (TRA) ...................................................................... 90