Renesas SH7781 用户手册
19. Display Unit (DU)
Rev.1.00 Jan. 10, 2008 Page 876 of 1658
REJ09B0261-0100
REJ09B0261-0100
19.3.21
DE Signal Start Register (DESR)
The DE signal start register (DESR) sets the rising edge position of the DE signal. The value is
retained during power-on reset and manual reset.
retained during power-on reset and manual reset.
R/W:
Internal update:
R/W:
Internal update:
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
30
Bit:
Initial value:
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
O
O
O
O
O
O
O
O
O
O
O
—
—
—
—
—
—
—
—
—
—
—
0
0
0
0
0
DES
—
—
—
—
—
0
1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
Bit:
Initial value:
Bit Bit
Name
Initial
Value R/W
Value R/W
Internal
Update Description
Update Description
31 to 11
⎯ All
0
R
⎯ Reserved
These bits are always read as 0. The write value
should always be 0.
should always be 0.
10 to 0
DES
Undefined R/W
Yes
DE Signal Start
The DE signal rising edge position should be set
in dot clock units relative to the falling edge of
the HSYNC signal.
in dot clock units relative to the falling edge of
the HSYNC signal.
The DE signal rises (setting + 1) cycles after the
falling edge of the HSYNC signal. Hence the DE
signal cannot be made to rise in the same cycle
as the falling edge of the HSYNC signal.
falling edge of the HSYNC signal. Hence the DE
signal cannot be made to rise in the same cycle
as the falling edge of the HSYNC signal.
During the vertical blanking interval the level is
fixed at low level.
fixed at low level.