Renesas 4513 用户手册
2-10
APPLICATION
2.1 I/O pins
4513/4514 Group User’s Manual
Table 2.1.6 connections of unused pins
Pin
X
OUT
VDCE
D
0
–D
5
D
6
/CNTR0
D
7
/CNTR1
P2
0
/S
CK
P2
1
/S
OUT
P2
2
/S
IN
P3
0
/INT0
P3
1
/INT1
P3
2
, P3
3
P4
0
/A
IN4
–P4
3
/A
IN7
P5
0
–P5
3
(Note 1)
A
IN0
/CMP0-
A
IN1
/CMP0+
A
IN2
/CMP1-
A
IN3
/CMP1+
P0
0
–P0
3
P1
0
–P1
3
Connection
Open (when using an external clock).
Connect to V
SS
.
Connect to V
SS
, or set the output latch to “0” and open.
Connect to V
SS
.
Connect to V
SS
, or set the output latch to “0” and open.
Connect to V
SS
, or set the output latch to “0” and open.
When the input mode is selected by software, pull-up to V
DD
through a resistor or
pull-down to V
SS
. When selecting the output mode, open.
Connect to V
SS
.
Open or connect to V
SS
(Note 2).
Open or connect to V
SS
(Note 2).
Notes 1: After system is released from reset, port P5 is in an input mode (direction register FR0 = 0000
2
)
2: When the P0
0
–P0
3
and P1
0
–P1
3
are connected to V
SS
, turn off their pull-up transistors (register
PU0i=“0”) and also invalidate the key-on wakeup functions (register K0i=“0”) by software. When
these pins are connected to V
these pins are connected to V
SS
while the key-on wakeup functions are left valid, the system fails
to return from RAM back-up state. When these pins are open, turn on their pull-up transistors
(register PU0i=“1”) by software, or set the output latch to “0.”
Be sure to select the key-on wakeup functions and the pull-up functions with every two pins. If
only one of the two pins for the key-on wakeup function is used, turn on their pull-up transistors
by software and also disconnect the other pin. (i = 0, 1, 2, or 3.)
(register PU0i=“1”) by software, or set the output latch to “0.”
Be sure to select the key-on wakeup functions and the pull-up functions with every two pins. If
only one of the two pins for the key-on wakeup function is used, turn on their pull-up transistors
by software and also disconnect the other pin. (i = 0, 1, 2, or 3.)
(Note in order to set the output latch to “0” and make pins open)
• After system is released from reset, a port is in a high-impedance state until the output latch of the port
• After system is released from reset, a port is in a high-impedance state until the output latch of the port
is set to “0” by software. Accordingly, the voltage level of pins is undefined and the excess of the supply
current may occur.
current may occur.
• To set the output latch periodically is recommended because the value of output latch may change by
noise or a program run away (caused by noise).
(Note in order to connect unused pins to V
SS
or V
DD
)
• To avoid noise, connect the unused pins to V
SS
or V
DD
at the shortest distance using a thick wire.