Renesas 4513 用户手册

1-56

4513/4514 Group User’s Manual

K0

3

K0

2

K0

1

K0

0

Key-on wakeup control register K0

PU0

3

PU0

2

PU0

1

PU0

0

Key-on wakeup not used

Key-on wakeup used

Key-on wakeup not used

Key-on wakeup used

Key-on wakeup not used

Key-on wakeup used

Key-on wakeup not used

Key-on wakeup used

Pins P1

2

 and P1

3

 key-on wakeup

control bit

Pins P1

0

 and P1

1

 key-on wakeup

control bit

Pins P0

2

 and P0

3

 key-on wakeup

control bit

Pins P0

0

 and P0

1

 key-on wakeup

control bit

at reset : 0000

2

at RAM back-up : state retained

0

1

0

1

0

1

0

1

Pull-up transistor OFF

Pull-up transistor ON

Pull-up transistor OFF

Pull-up transistor ON

Pull-up transistor OFF

Pull-up transistor ON

Pull-up transistor OFF

Pull-up transistor ON

Pins P1

2

 and P1

3

 pull-up transistor

control bit

Pins P1

0

 and P1

1

 pull-up transistor

control bit

Pins P0

2

 and P0

3

 pull-up transistor

control bit

Pins P0

0

 and P0

1

 pull-up transistor

control bit

R/W

Pull-up control register PU0

at reset : 0000

2

at RAM back-up : state retained

0

1

0

1

0

1

0

1

R/W

I1

3

I1

2

I1

1

I1

0

I2

3

I2

2

I2

1

I2

0

Not used

Interrupt valid waveform for INT0 pin/

return level selection bit (Note 2)

INT0 pin edge detection circuit control bit

INT0 pin

timer 1 control enable bit

This bit has no function, but read/write is enabled.

Falling waveform (“L” level of INT1 pin is recognized with the SNZI1

instruction)/“L” level

Rising waveform (“H” level of INT1 pin is recognized with the SNZI1

instruction)/“H” level

One-sided edge detected

Both edges detected

Disabled

Enabled

Not used

Interrupt valid waveform for INT1 pin/

return level selection bit (Note 3)

INT1 pin edge detection circuit control bit

INT1 pin

timer 3 control enable bit

Notes 1: “R” represents read enabled, and “W” represents write enabled.

2: When the contents of  I1

2

 is changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction.

3: When the contents of  I2

2

 is changed, the external interrupt request flag EXF1 may be set. Accordingly, clear EXF1 flag with the SNZ1 instruction.

Interrupt control register I1

R/W

at RAM back-up : state retained

at reset : 0000

2

This bit has no function, but read/write is enabled.

Falling waveform (“L” level of INT0 pin is recognized with the SNZI0

instruction)/“L” level

Rising waveform (“H” level of INT0 pin is recognized with the SNZI0

instruction)/“H” level

One-sided edge detected

Both edges detected

Disabled

Enabled

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Interrupt control register I2

R/W

at RAM back-up : state retained

at reset : 0000

2