IBM EM78M611E 用户手册
EM78M611E
Universal Serial Bus Series Microcontroller
Product Specification
(V1.11) 04.20.2007
•••• 27
(This specification is subject to change without further notice)
high state, then the “high pattern counter“ will increase; otherwise the “low pattern
counter” increases. As long as the signal state changes, the PDA will debounce signal
and load the value of pattern counter into the respectively register for the firmware to
read. For example, if the signal in P.92 is in “low” state, the low counter of P.92 will
count continuously until the state of the input signal in P.92 changes. When a state
change occurs (in this case, the signal changes from “low” to “high” state), the PDA will
take a time break (which is equal to the result of sampling interval multiplied by the
debounce length), to avoid possible noise. After the debounce length time, if the signal
remains in high state, the high pattern counter will start to count and load the low
pattern counter’s value into R10. At the same time, RB[6] is cleared to indicate that low
pattern is over.
counter” increases. As long as the signal state changes, the PDA will debounce signal
and load the value of pattern counter into the respectively register for the firmware to
read. For example, if the signal in P.92 is in “low” state, the low counter of P.92 will
count continuously until the state of the input signal in P.92 changes. When a state
change occurs (in this case, the signal changes from “low” to “high” state), the PDA will
take a time break (which is equal to the result of sampling interval multiplied by the
debounce length), to avoid possible noise. After the debounce length time, if the signal
remains in high state, the high pattern counter will start to count and load the low
pattern counter’s value into R10. At the same time, RB[6] is cleared to indicate that low
pattern is over.
The correlation between the control register value and debounce time are as follows:
DB.2
DB.1
DB.0
Debounce Time
0
0
0
0
0
0
1
Sampling clock
0
1
0
Sampling clock
×
2
0
1
1
Sampling clock
×
3
1
0
0
Sampling clock
×
4
1
0
1
Sampling clock
×
5
1
1
0
Sampling clock
×
6
1
1
1
Sampling clock
×
7
On the other hand, when the signal of P92 always remains “low”, the low pattern
counter of P92 will eventually overflow. Once the counter overflows, the content of the
counter will also be loaded into R10, that is, the register is written to 0xFF, and the
counter is reset to count from zero again.
counter of P92 will eventually overflow. Once the counter overflows, the content of the
counter will also be loaded into R10, that is, the register is written to 0xFF, and the
counter is reset to count from zero again.
If the hardware interrupt of PDA function is enabled, (IOCF[5] is equal to “1”), then the
program will go to 0x0001 to execute interrupt routine while the content of a pattern
counter is loaded into the register.
program will go to 0x0001 to execute interrupt routine while the content of a pattern
counter is loaded into the register.
The correlation between the value of control register and actual sampling rate are as
shown below
:
SR.2 SR.1 SR.0
Sampling Rate
(External oscillator frequency = 6MHz)
Sampling Rate
(External oscillator frequency = 12MHz)
0
0
0
N.A.
N.A.
0
0
1
N.A.
N.A.
0
1
0
1500 (Count / mSec)
N.A.
0
1
1
750 (Count / mSec)
1500 (Count/ mSec)
1
0
0
375 (Count / mSec)
750 (Count / mSec)
1
0
1
188 (Count / mSec)
375 (Count / mSec)
1
1
0
94 (Count / mSec)
188 (Count / mSec)
1
1
1
47 (Count / mSec)
94 (Count / mSec)