Motorola MC68VZ328 用户手册
DRAM Controller Operation
DRAM Controller
7-3
7.2
DRAM Controller Operation
This section describes the DRAM controller’s operation.
7.2.1
Address Multiplexing
The address multiplexer can support a wide variety of memory devices in either 8- or 16-bit mode. The
upper internal address lines from the CPU or LCD controller provide the row address, and the lower
internal address lines are used as the column address. This scheme enables the use of Fast Page Mode or
EDO RAM mode read accesses to the DRAM during LCD DMA cycles. The DRAM multiplexer also
supports different row and column configurations, depending on the arrangement of the DRAM rows and
columns and the data port size (8 or 16 bit) of the DRAM.
upper internal address lines from the CPU or LCD controller provide the row address, and the lower
internal address lines are used as the column address. This scheme enables the use of Fast Page Mode or
EDO RAM mode read accesses to the DRAM during LCD DMA cycles. The DRAM multiplexer also
supports different row and column configurations, depending on the arrangement of the DRAM rows and
columns and the data port size (8 or 16 bit) of the DRAM.
For 4 Mbyte (512K
×
8) DRAM, there are usually only 10 row addresses and 9 column addresses. For this
configuration in 8-bit mode, the internal address bus PA[8:0] is used for column addresses, and PA[18:9] is
used for row addresses. Similarly, if we use 16-bit DRAM with the same number of row and column
addresses, the column addresses require PA[9:1], and PA[19:10] is used for the row addresses.
used for row addresses. Similarly, if we use 16-bit DRAM with the same number of row and column
addresses, the column addresses require PA[9:1], and PA[19:10] is used for the row addresses.
The address multiplexing options are provided in Table 7-1 on page 7-4. The MC68VZ328’s DRAM
controller uses PA[8:1] as the column addresses for MD[7:0] and then allows software to select either PA0
or PA9 for column address MD8. Similar address selection options are provided for MD9 and MD10
column addresses, the MD0 row address, and the row addresses MD8 through MD12 .
controller uses PA[8:1] as the column addresses for MD[7:0] and then allows software to select either PA0
or PA9 for column address MD8. Similar address selection options are provided for MD9 and MD10
column addresses, the MD0 row address, and the row addresses MD8 through MD12 .
The MD[12:0] signals share the same address pins that output as nonmultiplexed addresses A[13:1] for
non-DRAM external accesses. Since the internal addresses (PA[13:1]) are present as the column address
selection from the DRAM address multiplexer, these addresses may be used as the nonmultiplexed
addresses A[13:1] for non-DRAM external accesses. This simplifies the overall multiplexing scheme for
the MC68VZ328.
non-DRAM external accesses. Since the internal addresses (PA[13:1]) are present as the column address
selection from the DRAM address multiplexer, these addresses may be used as the nonmultiplexed
addresses A[13:1] for non-DRAM external accesses. This simplifies the overall multiplexing scheme for
the MC68VZ328.
NOTE:
The A0 signal is not used as a DRAM address pin connection.
Table 7-1 on page 7-4 contains the address multiplexing options for the VZ pins listed. All the options are
programmed in the DRAM memory configuration (DRAMMC) register except as noted in the table. The
row labeled “Column Address Options” is used for Fast Page Mode and EDO RAM and is enabled when
the SDEN bit (bit 15) in the SDRAM control register (0xFFFFFC04) is 0. The row labeled “Column
Address Options Specific for SDRAM” is used for SDRAM and is enabled when the SDEN bit in the
SDRAM control register is 1.
programmed in the DRAM memory configuration (DRAMMC) register except as noted in the table. The
row labeled “Column Address Options” is used for Fast Page Mode and EDO RAM and is enabled when
the SDEN bit (bit 15) in the SDRAM control register (0xFFFFFC04) is 0. The row labeled “Column
Address Options Specific for SDRAM” is used for SDRAM and is enabled when the SDEN bit in the
SDRAM control register is 1.