Motorola MC68VZ328 用户手册
8-2
MC68VZ328 User’s Manual
LCD Controller Operation
Figure 8-1. LCD Controller Block Diagram
8.2
LCD Controller Operation
The LCD controller consists of CPU interface registers, control logic, a screen DMA controller, a line
buffer, cursor logic, frame rate control, and an LCD panel interface. Figure 8-1 illustrates how these blocks
are organized.
buffer, cursor logic, frame rate control, and an LCD panel interface. Figure 8-1 illustrates how these blocks
are organized.
The CPU interface registers provide control of different features of the LCD controller. Connected to the
CPU bus, the control logic provides the internal control and counting signals for other blocks in the LCD
controller. The DMA generates a bus request (BR) signal to the core, and when the bus is granted, it
performs a few memory bursts to fill up the line buffer. The number of DMA clock cycles in each burst is
the programmable number of clocks per transfer, which makes it easier to support a system with memory
with different speed grades.
CPU bus, the control logic provides the internal control and counting signals for other blocks in the LCD
controller. The DMA generates a bus request (BR) signal to the core, and when the bus is granted, it
performs a few memory bursts to fill up the line buffer. The number of DMA clock cycles in each burst is
the programmable number of clocks per transfer, which makes it easier to support a system with memory
with different speed grades.
The line buffer collects display data from system memory during DMA cycles and outputs it to the cursor
logic block. The input is synchronized with the fast DMA clock, while the output is synchronized to the
relatively slow LCD pixel clock. The cursor control logic, when enabled, is used to generate a
block-shaped cursor on the display screen. The height and width of the cursor can be changed, as long as a
number between 1 and 31 is used. The cursor may also be completely black or reversed video, and the
blinking rate is adjustable when the BKEN bit in the LCD blink control (LBLKC) register is set.
logic block. The input is synchronized with the fast DMA clock, while the output is synchronized to the
relatively slow LCD pixel clock. The cursor control logic, when enabled, is used to generate a
block-shaped cursor on the display screen. The height and width of the cursor can be changed, as long as a
number between 1 and 31 is used. The cursor may also be completely black or reversed video, and the
blinking rate is adjustable when the BKEN bit in the LCD blink control (LBLKC) register is set.
Frame rate control is mainly used for grayscale displays and generates a maximum of 16 grayscale levels
out of 16 density levels, as shown in Table 8-1 on page 8-7. The density level corresponds to the number of
times that a pixel is turned on when the display is refreshing.
out of 16 density levels, as shown in Table 8-1 on page 8-7. The density level corresponds to the number of
times that a pixel is turned on when the display is refreshing.
Since crystal formulations and driving
voltage may vary, the quality of the grayscale can be fine-tuned by programming the LCD gray palette
mapping register (LGPMR).
mapping register (LGPMR).
Address
Bus
Data
Bus
DMACLK
Pixel
Clock
OE
CSxx
LCD Bias
Voltage Control
Voltage Control
SIM
CPU
CPU
Interface
Registers
Control
Logic
Screen
DMA
Line Buffer
PWM
Cursor
Logic
Frame
Rate
Control
LCD
Driver
LCD
Interface
LCD Controller
BR
BG
System
Memory