Motorola MC68VZ328 用户手册
8-8
MC68VZ328 User’s Manual
LCD Controller Operation
8.2.3
Using Low-Power Mode
Some panels may have a PANEL_OFF signal, which is used to turn off the panel for low-power mode. In
an MC68VZ328 system, this signal is not supported, but can be easily implemented using a parallel I/O
pin. The software can be programmed to achieve PANEL_OFF by using parallel I/O in the following
sequence:
an MC68VZ328 system, this signal is not supported, but can be easily implemented using a parallel I/O
pin. The software can be programmed to achieve PANEL_OFF by using parallel I/O in the following
sequence:
1.
Drive the LCD bias voltage to 0 V.
2.
Set the LCDON bit to 0 in the LCD clocking control (LCKCON) register, turning off the
LCD controller.
LCD controller.
To turn the LCD controller back on, follow the following steps:
1.
Set the LCDON bit to 1 in the LCKCON register, which turns on the LCD controller.
2.
Pause for 1 or 2 ms.
3.
Drive the LCD bias voltage to +15 V or -15 V.
When setting the LCDON bit in the CLKCON register to 0, the LCD controller will enter low-power mode
by stopping its own pixel clock prior to the next line buffer fill DMA. Further screen DMA and display
refresh operations will then be halted in this mode. When the LCD controller is turned back on, DMA and
screen refresh activities will resume synchronously.
by stopping its own pixel clock prior to the next line buffer fill DMA. Further screen DMA and display
refresh operations will then be halted in this mode. When the LCD controller is turned back on, DMA and
screen refresh activities will resume synchronously.
8.2.4
Using the DMA Controller
The LCD DMA controller is a fly-by-type, 16-bit-wide, fast data transfer device. Since the LCD screen has
to be continuously refreshed at a rate of 50 Hz to 70 Hz, the pixel bits in the memory will be read and
transferred to the corresponding pixels on the screen. To minimize bus obstruction, a burst type and fly-by
transfer is required. Each cycle is evenly distributed across the time frame. Every time the internal line
buffer needs data, it asserts the BR signal to request the bus from the core. Once the core grants the bus
(BG is asserted), the DMA controller gets control of the bus signal and issues a number of words read from
memory. The read data is then internally passed to the internal pixel buffer. During the LCD access cycles,
output enable and chip-select signals for the corresponding system memory chip are asserted by the
chip-select logic inside the system integration module. It is possible to minimize bus bandwidth
obstruction by using zero LCD access wait-states (one clock per access).
to be continuously refreshed at a rate of 50 Hz to 70 Hz, the pixel bits in the memory will be read and
transferred to the corresponding pixels on the screen. To minimize bus obstruction, a burst type and fly-by
transfer is required. Each cycle is evenly distributed across the time frame. Every time the internal line
buffer needs data, it asserts the BR signal to request the bus from the core. Once the core grants the bus
(BG is asserted), the DMA controller gets control of the bus signal and issues a number of words read from
memory. The read data is then internally passed to the internal pixel buffer. During the LCD access cycles,
output enable and chip-select signals for the corresponding system memory chip are asserted by the
chip-select logic inside the system integration module. It is possible to minimize bus bandwidth
obstruction by using zero LCD access wait-states (one clock per access).
8.2.4.1
Bus Bandwidth Calculation Example
Since LCD screen refresh occurs periodically, the load that the LCD controller puts on the host data bus
becomes an important consideration to the high-performance handheld system designer. There are many
issues involved in estimating bandwidth overhead to the data bus. Consider a typical scenario:
becomes an important consideration to the high-performance handheld system designer. There are many
issues involved in estimating bandwidth overhead to the data bus. Consider a typical scenario:
•
Screen size: 320
×
240 pixels
•
Bits per pixel: 2 bits per pixel
•
Screen refresh rate: 60 Hz
•
System clock: 16.58 MHz
•
Host bus size: 16 bit
•
DMA access cycle: 2 cycles per 16-bit word
The following T
l
period is used by the LCD controller to update one line of the screen: