Motorola MC68VZ328 用户手册
14-2
MC68VZ328 User’s Manual
Serial Operation
The UART 2 module is an enhanced version of the UART 1. The features listed above are enhanced by the
following modifications in the UART 2 module:
following modifications in the UART 2 module:
•
The size of the RxFIFO and TxFIFO is increased to 64 bytes each.
•
Both the RxFIFO and TxFIFO half mark levels are user selectable.
•
The RTS signal can be triggered by either a near RxFIFO full condition or at the level defined by
the RxFIFO level marker, rather than the RxFIFO half-full bit as is UART 1.
the RxFIFO level marker, rather than the RxFIFO half-full bit as is UART 1.
Both the UART 1 and UART 2 modules perform all of the normal operations associated with start-stop
asynchronous communication. Serial data is transmitted and received at standard bit rates using the
internal baud rate generator. For those applications that need other bit rates, a 1x clock mode is available
providing a data-bit clock. Figure 14-1 illustrates a high-level block diagram of both UART modules.
asynchronous communication. Serial data is transmitted and received at standard bit rates using the
internal baud rate generator. For those applications that need other bit rates, a 1x clock mode is available
providing a data-bit clock. Figure 14-1 illustrates a high-level block diagram of both UART modules.
Figure 14-1. UART Simplified Block Diagram
14.2
Serial Operation
The UART modules have two modes of operation—NRZ and IrDA. Section 14.2.1, “NRZ Mode,” and
Section 14.2.2, “IrDA Mode,” describe these two modes of operation.
Section 14.2.2, “IrDA Mode,” describe these two modes of operation.
14.2.1
NRZ Mode
The nonreturn to zero (NRZ) mode is primarily associated with RS-232. Each character is transmitted as a
frame delimited by a start bit at the beginning and a stop bit at the end. Data bits are transmitted least
significant bit first, and each bit occupies a period of time equal to 1 full bit. If parity is used, the parity bit
is transmitted after the most significant bit. Figure 14-2 on page 14-3 illustrates a character in NRZ mode.
frame delimited by a start bit at the beginning and a stop bit at the end. Data bits are transmitted least
significant bit first, and each bit occupies a period of time equal to 1 full bit. If parity is used, the parity bit
is transmitted after the most significant bit. Figure 14-2 on page 14-3 illustrates a character in NRZ mode.
CPU
Baud Rate
Generator
Receiver
RxFIFO
TxFIFO Transmitter
Serial
Interface
Infrared
Interface
UCLK
CTS
x
RTS
x
TxD
x
RxD
x