Motorola MC68VZ328 用户手册
14-6
MC68VZ328 User’s Manual
UART Operation
14.3.2
Receiver Operation
The receiver block of the UART accepts a serial data stream, converting it into parallel characters. The
receiver operates in two modes—asynchronous and synchronous. In asynchronous mode, it searches for a
start bit, qualifies it, and then samples the succeeding data bits at the perceived bit center. Jitter tolerance
and noise immunity are provided by sampling 16 times per bit and using a voting circuit to enhance
sampling. IrDA operation must use asynchronous mode. In synchronous mode, RXDx is sampled on each
rising edge of the bit clock, which is generated by the UART module or supplied externally. When a start
bit is identified, the remaining bits are shifted in and loaded into the FIFO.
receiver operates in two modes—asynchronous and synchronous. In asynchronous mode, it searches for a
start bit, qualifies it, and then samples the succeeding data bits at the perceived bit center. Jitter tolerance
and noise immunity are provided by sampling 16 times per bit and using a voting circuit to enhance
sampling. IrDA operation must use asynchronous mode. In synchronous mode, RXDx is sampled on each
rising edge of the bit clock, which is generated by the UART module or supplied externally. When a start
bit is identified, the remaining bits are shifted in and loaded into the FIFO.
If parity is enabled, the parity bit is checked and its status is reported in the URX register. Similarly, frame
errors, breaks, and overruns are checked and reported. The 4 character status bits in the high byte (bits
11–8) of the URX register are valid only when read as a 16-bit word with the received character byte.
errors, breaks, and overruns are checked and reported. The 4 character status bits in the high byte (bits
11–8) of the URX register are valid only when read as a 16-bit word with the received character byte.
14.3.2.1
Rx FIFO Buffer Operation
As with the transmitter, the receiver FIFO is flexible. If the software being used has short interrupt latency
time, the FIFO FULL interrupt in the URX register can be enabled. The FIFO has no remaining space
available when this interrupt is generated. If the DATA READY bit in the URX register indicates that
more data is remaining in the FIFO, the FIFO can then be emptied byte by byte. If the software has a
longer latency time, the FIFO HALF interrupt of the URX register can be used. This interrupt is generated
when no more than 4 empty bytes remain in the FIFO. If the FIFO is not needed, the DATA READY
interrupt should be used. This interrupt is generated when one or more characters are present in the FIFO.
The OLD DATA bit in the URX register indicates that there is data in the FIFO and that the receive line
has been idle for more than 30 bit times. This is useful in determining the end of a block of characters.
time, the FIFO FULL interrupt in the URX register can be enabled. The FIFO has no remaining space
available when this interrupt is generated. If the DATA READY bit in the URX register indicates that
more data is remaining in the FIFO, the FIFO can then be emptied byte by byte. If the software has a
longer latency time, the FIFO HALF interrupt of the URX register can be used. This interrupt is generated
when no more than 4 empty bytes remain in the FIFO. If the FIFO is not needed, the DATA READY
interrupt should be used. This interrupt is generated when one or more characters are present in the FIFO.
The OLD DATA bit in the URX register indicates that there is data in the FIFO and that the receive line
has been idle for more than 30 bit times. This is useful in determining the end of a block of characters.
When IrDA mode is enabled, the receiver expects narrow (1.63
µ
s at a minimum) pulses for each zero bit
received. Otherwise, normal NRZ is expected. An infrared transceiver directly connected to the RXDx pin
transforms the infrared signal into an electrical signal. Polarity is programmable so that RXDx can be
connected directly to an external IrDA transceiver.
transforms the infrared signal into an electrical signal. Polarity is programmable so that RXDx can be
connected directly to an external IrDA transceiver.
14.3.3
Baud Rate Generator Operation
The baud generator provides the bit clocks to the transmitter and receiver blocks. It consists of two
prescalers, an integer prescaler, and a second non-integer prescaler, as well as a 2
prescalers, an integer prescaler, and a second non-integer prescaler, as well as a 2
n
divider. Figure 14-4 on
page 14-7 illustrates a block diagram of the baud rate generator.