Motorola MC68VZ328 用户手册
14-26
MC68VZ328 User’s Manual
Programming Model
14.4.12
UART 2 Miscellaneous Register
The UART 2 miscellaneous (UMISC2) register contains miscellaneous bits to control test features of the
UART 2 module. Some bits, however, are only used for factory testing and should not be used. The bit
position assignments for this register are shown in the following register display. The settings for this
register are described in Table 14-14.
UART 2 module. Some bits, however, are only used for factory testing and should not be used. The bit
position assignments for this register are shown in the following register display. The settings for this
register are described in Table 14-14.
UMISC2
UART 2 Miscellaneous Register
0x(FF)FFF918
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
BIT
0
BA
UD
TES
T
CLK
SR
C
FOR
CE
PER
R
LO
OP
BAU
D
RES
ET
IR
TES
T
RTS
2
CO
NT
RT
S2
IR
DA
EN
EN
IRD
A
LO
OP
RX
PO
PO
L
TX
PO
L
TYPE
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
Table 14-14. UART 2 Miscellaneous Register Description
Name
Description
Setting
BAUD
TEST
Bit 15
TEST
Bit 15
Baud Rate Generator Testing—This bit puts the baud rate
generator in test mode. The integer and non-integer prescal-
ers, as well as the divider, are broken into 4-bit nibbles for test-
ing. This bit should remain 0 for normal operation.
generator in test mode. The integer and non-integer prescal-
ers, as well as the divider, are broken into 4-bit nibbles for test-
ing. This bit should remain 0 for normal operation.
0 = Normal mode.
1 = Test mode.
1 = Test mode.
CLKSRC
Bit 14
Bit 14
Clock Source—This bit selects the source of the 1x bit clock
for transmission and reception. When this bit is high, the bit
clock is derived directly from the UCLK pin (it must be config-
ured as an input). When it is low (normal), the bit clock is sup-
plied by the baud rate generator. This bit allows high-speed
synchronous applications, in which a clock is provided by the
external system.
for transmission and reception. When this bit is high, the bit
clock is derived directly from the UCLK pin (it must be config-
ured as an input). When it is low (normal), the bit clock is sup-
plied by the baud rate generator. This bit allows high-speed
synchronous applications, in which a clock is provided by the
external system.
0 = Bit clock is generated by the
baud rate generator.
1 = Bit clock is supplied by the
UCLK pin.
FORCE
PERR
Bit 13
PERR
Bit 13
Force Parity Error—When this bit is high, it forces the trans-
mitter to generate parity errors, if parity is enabled. This bit is
for system debugging.
mitter to generate parity errors, if parity is enabled. This bit is
for system debugging.
0 = Generate normal parity.
1 = Generate inverted parity (error).
1 = Generate inverted parity (error).
LOOP
Bit 12
Bit 12
Loopback—This bit controls loopback for system testing pur-
poses. When this bit is high, the receiver input is internally con-
nected to the transmitter and ignores the RXD2 pin. The TXD2
pin is unaffected by this bit.
poses. When this bit is high, the receiver input is internally con-
nected to the transmitter and ignores the RXD2 pin. The TXD2
pin is unaffected by this bit.
0 = Normal receiver operation.
1 = Internally connects the
1 = Internally connects the
transmitter output to the
receiver input.
receiver input.
BAUD
RESET
Bit 11
RESET
Bit 11
Baud Rate Generator Reset—This bit resets the baud rate
generator counters.
generator counters.
0 = Normal operation.
1 = Reset baud counters.
1 = Reset baud counters.
IRTEST
Bit 10
Bit 10
Infrared Testing—This bit connects the output of the IrDA cir-
cuitry to the TXD2 pin. This provides test visibility to the IrDA
module.
cuitry to the TXD2 pin. This provides test visibility to the IrDA
module.
0 = Normal operation.
1 = IrDA test mode.
1 = IrDA test mode.
Reserved
Bits 9–8
Bits 9–8
Reserved
These bits are reserved and should
be set to 0.
be set to 0.