Motorola MC68VZ328 用户手册
16-10
MC68VZ328 User’s Manual
Typical Design Programming Example
16.2.4
In-Circuit Emulation Module Status Register
The in-circuit emulation module status register (ICEMSR) is used to determine the source of an interrupt.
The bit assignments for the ICE module status register are shown in the following register display. The
settings for the bits are described in Table 16-6.
The bit assignments for the ICE module status register are shown in the following register display. The
settings for the bits are described in Table 16-6.
ICEMSR
ICE Module Status Register
0x(FF)FFFFFD0E
16.3
Typical Design Programming Example
Figure 16-2 on page 16-11 illustrates an example of a typical emulator design. It is a simple and low-cost
design that uses the MC68VZ328 as the processor to be emulated. Other functional units include the host
control to the PC or workstation via an RS-232 or a dedicated parallel interface, an optional address
comparator for extra breakpoint expansion, optional map FPGA for emulation memory remapping, a data
bus MUX for hardware breakpoint insertion, and a MC68VZ328 pin-out extension to connect to the
solder-on emulator pod. The entire MC68VZ328 bus should be buffered using level-shifting buffers when
the emulator is designed in 5 V and the processor is running at 3.3 V.
design that uses the MC68VZ328 as the processor to be emulated. Other functional units include the host
control to the PC or workstation via an RS-232 or a dedicated parallel interface, an optional address
comparator for extra breakpoint expansion, optional map FPGA for emulation memory remapping, a data
bus MUX for hardware breakpoint insertion, and a MC68VZ328 pin-out extension to connect to the
solder-on emulator pod. The entire MC68VZ328 bus should be buffered using level-shifting buffers when
the emulator is designed in 5 V and the processor is running at 3.3 V.
BIT 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
BIT 0
EMUEN
BBIRQ
BRKIRQ
EMIRQ
TYPE
rw
rw
rw
rw
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x0000
Table 16-6. ICE Module Status Register Description
Name
Description
Setting
Reserved
Bits 15–4
Bits 15–4
Reserved
These bits are reserved and should be
set to 0.
set to 0.
EMUEN
Bit 3
Bit 3
Emulation Enable—This bit, when set, enables ICE
mode.
mode.
0 = Normal mode.
1 = ICE mode.
1 = ICE mode.
BBIRQ
Bit 2
Bit 2
Bus Break Interrupt Detected—This bit is set when a
bus breakpoint is hit. Writing a 1 to this bit clears it.
bus breakpoint is hit. Writing a 1 to this bit clears it.
0 = Bus breakpoint has not occurred.
1 = Bus breakpoint has occurred.
1 = Bus breakpoint has occurred.
BRKIRQ
Bit 1
Bit 1
Line Vector Fetch Detected—This bit is set when a pro-
gram breakpoint is hit. Writing a 1 to this bit clears it.
gram breakpoint is hit. Writing a 1 to this bit clears it.
0 = Program breakpoint has not
occurred.
1 = Program breakpoint has occurred.
EMIRQ
Bit 0
Bit 0
EMUIRQ Falling Edge Detected—This bit is set when
the EMUIRQ pin is going from high to low. Writing a 1 to
this bit clears it.
the EMUIRQ pin is going from high to low. Writing a 1 to
this bit clears it.
See description.