Motorola MC68VZ328 用户手册
Plug-in Emulator Design Example
In-Circuit Emulation
16-13
Figure 16-3. Plug-in Emulator Design Example
Although there is only one hardware breakpoint in this design, all other software breakpoints can be
generated by replacing the memory content of the A0 instruction. The EMUCS is decoded by a PAL to
generate chip-select signals to the UART (68HC681) or ADI interface and the debug RAM or ROM or
both RAM and ROM. The emulation module is buffered with 3.3 V to 5.0 V buffers so that it can
communicate with the PC without causing any problems.
generated by replacing the memory content of the A0 instruction. The EMUCS is decoded by a PAL to
generate chip-select signals to the UART (68HC681) or ADI interface and the debug RAM or ROM or
both RAM and ROM. The emulation module is buffered with 3.3 V to 5.0 V buffers so that it can
communicate with the PC without causing any problems.
The entire emulation module only uses 29 pins, including a ground signal. A very low-cost cable can be
built to ship with the software debugger package. These pins can remain on the production version of the
system board for production testing, as well as diagnostic and failure analysis.
built to ship with the software debugger package. These pins can remain on the production version of the
system board for production testing, as well as diagnostic and failure analysis.
Host
Interface
RS-232/ADI
On-Board
Memory
16K Debug
EMUCS
D[15:0]
MC68VZ328
CPU
CSxx
ROM
Emulation Module
68HC681
PC
D[15:8] / A[13:0]
EMUIRQ
PAL
A[15:14]
RAM/ROM
or
ADI
DTACK
16K Debug
SRAM
/3.3 V
3.3 V to 5 V Buffer
/5 V
Buffer
D[15:0]