Motorola MC68VZ328 用户手册

2-3

Power

V

DD

9

5

Ground

V

SS

16

28

Regulator output

LV

DD

5

1

Clocks/PCIO

XTAL, EXTAL, CLKO/PF2

3

3

System control

RESET

1

1

Address bus/PFIO

PF[3:6]/A[23:20], A[19:14], A0/PG1, 
MA[15:0]/A[16:1]

24

24

Lower data bus/PAIO

PA[7:0]/D[7:0]

8

8

Upper data bus

D[15:8]

8

8

Bus control/PCIO/PEIO/
PKIO

BUSW/DTACK/PG0, OE, LWE/LB, UWE/UB, 
PE3/DWE/UCLK, PK2/LDS, PK3/UDS, PK1/RW

8

8

Interrupt controller/PMIO

INT0/PD0, INT1/PD1, INT2/PD2, INT3/PD3, 
IRQ1/PD4, IRQ2/PD5, IRQ3/PD6, IRQ6/PD7, 
IRQ5/PF1

9

9

LCD controller/PCIO

LACD/PC7, LCLK/PC6, LLP/PC5, LFLM/PC4, 
LD[7:4]/PK[7:4], LD[3:0]/PC[3:0], LCON-
TRAST/PF0

13

13

UART1/PEIO, UART2/PJIO

PE4/RXD1, PE5/TXD1, PE6/RTS1, PE7/CTS1, 
PJ4/RXD2, PJ5/TXD2, PJ6/RTS2, PJ7/CTS2

8

8

Timer/PBIO

TOUT/TIN/PB6

1

1

Pulse-width modulator/PBIO

PWMO1/PB7 (PM5/DATA_READY/PWMO2)

1

1

Master SPI/PEIO, config-
urable SPI/PJIO/PKIO

SPITXD/PE0, SPIRXD/PE1, SPICLK2/PE2,
PJ0/MOSI, PJ1/MISO, PJ2/SPICLK1, PJ3/SS, 
PK0/DATA_READY/PWMO2

8

8

Chip-select, 
EDO RAM/PBIO, PMIO

CSA[1:0]/PF7, CSB[1:0]/PB[1:0]/SDWE, 
CSC[1:0]/PB[3:2]/RAS[1:0], 
CSD[1:0]/PB[5:4]/CAS[1:0], PM5/DMOE

9

9

SDRAM/PMIO

PM0/SDCLK, PM1/SDCE, PM2/DQMH, 
PM3/DQML, PM4/SDA10, (SDWE, SDCAS[1:0], 
SDRAS[1:0] )—multiplexed with chip-select sig-
nals

5

5

Emulator pins

EMUIRQ/PG2, EMUBRK/PG5, HIZ/P/D/PG3, 
EMUCS/PG4

4

4

No connect pins

NC

4

0