Motorola MC68VZ328 用户手册
2-8
MC68VZ328 User’s Manual
Timer Signals
•
LCONTRAST/PF0—LCD Contrast and Port F bit 0. This output is generated by the pulse-width
modulator (PWM) inside the LCD controller to adjust the supply voltage to the LCD panel. This
pin can also be programmed as an I/O port. This pin defaults to GPIO input pulled high.
modulator (PWM) inside the LCD controller to adjust the supply voltage to the LCD panel. This
pin can also be programmed as an I/O port. This pin defaults to GPIO input pulled high.
2.9
UART 1 and UART 2 Controller Signals
There are two Universal Asynchronous Receive Transmit (UART) modules in the MC68VZ328. This
section describes the signals that are used to interface with external serial devices.
section describes the signals that are used to interface with external serial devices.
•
RXD1/PE4, RXD2/PJ4—UART 1 and UART 2 Receive Data or Port E bit 4 and Port J bit 4. RXD
is the receiver serial input. During normal operation, NRZ data is expected, but in IrDA mode, a
narrow pulse of 1.6 µs minimum is expected for each zero bit received. External circuitry must be
used to convert the IrDA signal to an electrical signal. RS-232 applications need an external RS-232
receiver to convert voltage levels. These pins default to GPIO input pulled high.
is the receiver serial input. During normal operation, NRZ data is expected, but in IrDA mode, a
narrow pulse of 1.6 µs minimum is expected for each zero bit received. External circuitry must be
used to convert the IrDA signal to an electrical signal. RS-232 applications need an external RS-232
receiver to convert voltage levels. These pins default to GPIO input pulled high.
•
TXD1/PE5, TXD2/PJ5—UART 1 and UART 2 Transmit Data or Port E bit 5 and Port J bit 5. TXD
is the transmitter serial output. During normal operation, they output NRZ data signals. In IrDA
mode, they output a selectable pulse width of three-sixteenths bit period or 1.6 µs minimum bit
period for each zero bit transmitted. For RS-232 applications, this pin must be connected to an
RS-232 transmitter. For IrDA applications, this pin can directly drive an IrDA LED. These pins
default to GPIO input pulled high.
is the transmitter serial output. During normal operation, they output NRZ data signals. In IrDA
mode, they output a selectable pulse width of three-sixteenths bit period or 1.6 µs minimum bit
period for each zero bit transmitted. For RS-232 applications, this pin must be connected to an
RS-232 transmitter. For IrDA applications, this pin can directly drive an IrDA LED. These pins
default to GPIO input pulled high.
•
RTS1/PE6, RTS2/PJ6—UART 1 and UART 2 Request to Send or Port E bit 6 and Port J bit 6. RTS
indicates that it is ready to receive data by asserting this pin (low). This pin would be connected to
the far-end transmitter’s CTS pin. When the receiver detects a pending overrun, it negates this pin.
These pins default to GPIO input pulled high.
indicates that it is ready to receive data by asserting this pin (low). This pin would be connected to
the far-end transmitter’s CTS pin. When the receiver detects a pending overrun, it negates this pin.
These pins default to GPIO input pulled high.
•
CTS1/PE7, CTS2/PJ7—UART 1 and UART 2 Clear to Send or Port E bit 7 and Port J bit 7. CTS
controls the transmitter. Normally, the transmitter waits until this signal is active (low) before a
character is transmitted. If the NOCTSx bit is set in the UTX register, the transmitter sends a
character whenever a character is ready to transmit. These pins default to GPIO input pulled high.
controls the transmitter. Normally, the transmitter waits until this signal is active (low) before a
character is transmitted. If the NOCTSx bit is set in the UTX register, the transmitter sends a
character whenever a character is ready to transmit. These pins default to GPIO input pulled high.
2.10
Timer Signals
There are several external timer and clock signal functions available using the MC68VZ328. This section
describes the signals and how they are programmed.
describes the signals and how they are programmed.
•
TOUT/TIN/PB6—Timer 1 Output, Timer 1 Input, or Port B bit 6. TOUT can be programmed to
toggle or generate a pulse of 1-system-clock duration when the timer/counter reaches a reference
value. TIN is used as the external clock source of Timer 1 or used as a capture function. This pin
defaults to GPIO input pulled high.
toggle or generate a pulse of 1-system-clock duration when the timer/counter reaches a reference
value. TIN is used as the external clock source of Timer 1 or used as a capture function. This pin
defaults to GPIO input pulled high.
•
UCLK/DWE/PE3—UART Clock input/output, DRAM Write-Enable, or Port E bit 3. The UCLK
function is selected when DWE is disabled and PESEL3 is written 0. The direction of UCLK is
controlled by the UCLKDIR bit of UART 1 and UART 2. For UCLK output, the UCLK bit of
peripheral control register selects the clock output signal from UART 1 or UART 2. This pin
defaults to GPIO input pulled high.
function is selected when DWE is disabled and PESEL3 is written 0. The direction of UCLK is
controlled by the UCLKDIR bit of UART 1 and UART 2. For UCLK output, the UCLK bit of
peripheral control register selects the clock output signal from UART 1 or UART 2. This pin
defaults to GPIO input pulled high.