Motorola MC68VZ328 用户手册
4-10
MC68VZ328 User’s Manual
Introduction to the Power Control Module
4.4.2
PLL Frequency Select Register
The PLL frequency select register (PLLFSR) controls the two dividers of the dual-modulus counter. It also
contains the write-protect bit for the QC and PC counters and the CLK32 status bit. Although PLLFSR
register can be accessed in bytes, it should always be written as a 16-bit word. The settings for each bit and
field in the register is described in Table 4-4.
contains the write-protect bit for the QC and PC counters and the CLK32 status bit. Although PLLFSR
register can be accessed in bytes, it should always be written as a 16-bit word. The settings for each bit and
field in the register is described in Table 4-4.
PLLFSR
PLL Frequency Select Register
0x(FF)FFF202
4.5
Introduction to the Power Control Module
The purpose of the power control module (PCM) is to optimize the power consumption of the FLX68000
CPU by turning the CPU off for a programmed number of clock pulses. The CPU consumes more power
than any component in the MC68VZ328, so to conserve power while the CPU is relatively idle, the PCM
can disable the CPU clock or apply the clock in bursts. When the MC68VZ328 is in one of these
reduced-power modes, it is restored to normal operation by a wake-up event. When this occurs, the clock is
immediately enabled, allowing the CPU to service the request. The DMA controller is not affected by the
PCM having full access to the bus while the CPU is idle, keeping the LCD screen refreshed.
CPU by turning the CPU off for a programmed number of clock pulses. The CPU consumes more power
than any component in the MC68VZ328, so to conserve power while the CPU is relatively idle, the PCM
can disable the CPU clock or apply the clock in bursts. When the MC68VZ328 is in one of these
reduced-power modes, it is restored to normal operation by a wake-up event. When this occurs, the clock is
immediately enabled, allowing the CPU to service the request. The DMA controller is not affected by the
PCM having full access to the bus while the CPU is idle, keeping the LCD screen refreshed.
BIT 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
BIT 0
CLK32
PROT
QC
PC
TYPE
r
rw*
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
RESET
0
0
0
0
0
0
1
1
0
1
0
0
0
1
1
1
0x0347
*This bit can be set by software but is cleared only by reset.
Table 4-4. PLL Frequency Select Register Settings
Name Description
Setting
CLK32
Bit 15
Bit 15
Clock32 Status—This read-only bit indicates
the status of the CLK32 clock signal. The bit
switches with each cycle of the CLK32 clock.
the status of the CLK32 clock signal. The bit
switches with each cycle of the CLK32 clock.
0 = CLK32 low.
1 = CLK32 high.
1 = CLK32 high.
PROT
Bit 14
Bit 14
Protect Bit—This bit write protects the QC
and PC fields of the PLLFSR. After this bit is
set by software, the register is write protected
until a reset clears this bit.
and PC fields of the PLLFSR. After this bit is
set by software, the register is write protected
until a reset clears this bit.
0 = PLLFSR is not protected.
1 = PLLFSR is write protected.
1 = PLLFSR is write protected.
Reserved
Bits 13–12
Bits 13–12
Reserved
These bits are reserved and must remain at
their default value.
their default value.
QC
Bits 11–8
Bits 11–8
Q Counter—This field contains the Q value
that is used by the PLL to produce the
PLLCLK.
that is used by the PLL to produce the
PLLCLK.
Field value range is 1 < Q < 14.
PC
Bits 7–0
Bits 7–0
P Counter—This field contains the P value
that is used by the PLL to produce the
PLLCLK.
that is used by the PLL to produce the
PLLCLK.
Field value range is P > Q + 1.