Motorola MVME2300 Series 用户手册
Raven Registers
http://www.motorola.com/computer/literature
2-41
2
MERAD
MPC Error Address. This register captures the MPC
address when the MATO bit is set in the MERST register.
It captures the PCI address when the SMA or RTA bits are
set in the MERST register. Its contents are not defined
when the PERR or SERR bits are set in the MERST
register.
address when the MATO bit is set in the MERST register.
It captures the PCI address when the SMA or RTA bits are
set in the MERST register. Its contents are not defined
when the PERR or SERR bits are set in the MERST
register.
MPC Error Attribute Register - MERAT
If the PERR or SERR bits are set in the MERST register, the contents of
the MERAT register are zero. If the MATO bit is set, the register is defined
by the following figure:
the MERAT register are zero. If the MATO bit is set, the register is defined
by the following figure:
MIDx
MPC Master ID. Contains the ID of the MPC master
which originated the transfer in which the error occurred.
The encoding scheme is identical to that used in the GCSR
register.
which originated the transfer in which the error occurred.
The encoding scheme is identical to that used in the GCSR
register.
TBST
Transfer Burst. This bit is set when the transfer in which
the error occurred was a burst transfer.
the error occurred was a burst transfer.
TSIZx
Transfer Size. Contains the transfer size of the MPC
transfer in which the error occurred.
transfer in which the error occurred.
TTx
Transfer Type. Contains the transfer type of the MPC
transfer in which the error occurred.
transfer in which the error occurred.
Address
$FEFF002C
Bit
0 1 2 3 4 5 6 7 8 9
1
0
0
1
1
1
1
2
2
1
3
3
1
4
4
1
5
5
1
6
6
1
7
7
1
8
8
1
9
9
2
0
0
2
1
1
2
2
2
2
3
3
2
4
4
2
5
5
2
6
6
2
7
7
2
8
8
2
9
9
3
0
0
3
1
1
Name
MERAT
MI
D
D
1
MI
D
D
0
TB
S
S
T
T
S
IZ0
T
S
IZ1
T
S
IZ2
TT
0
0
TT
1
1
TT
2
2
TT
3
3
TT
4
4
Operation
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Reset
$00
$00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0