Motorola MVME2300 Series 用户手册

Functional Description

http://www.motorola.com/computer/literature

3-19

The Falcon pair performs refreshes by doing a burst of four RAS_ cycles 
approximately once every 30

µ

s. This increases to once every 15

µ

s when 

certain DRAM devices are used. (The refresh rate is controlled by the 
ram_fref bit in the status registers.) RAS_ is asserted to blocks A and B 
during the first cycle, to blocks C and D during the second cycle, back to 
blocks A and B during the third cycle and to blocks C and D during the 
fourth cycle. Along with RAS, the Falcon pair also asserts CAS_ (with 
OE_ then WE_) to one of the blocks during one of the four cycles. This 
forms a read-modify-write which is a scrub cycle to that location. 

After the second and fourth cycles, the DRAM row address increments by 
one. When it reaches all 1s, it rolls over and starts anew at 0. Each time the 
row address rolls over, the block that is scrubbed toggles between A/C and 
B/D. Every second time the row address rolls over, which of the 4 cycles 
that is a scrub changes from 1st to 2nd, from 2nd to 3rd, from 3rd to 4th, 
or from 4th to 1st. Every eighth time that the row address rolls over, the 
column address increments by 1. When the column address reaches all 
ones, it rolls over and starts anew at 0. Each time the column address rolls 
over, the SC1, SC0 bits in the scrub/refresh register increment by 1. 

Note that an entire refresh of DRAM is achieved every time the row 
address rolls over, and that an entire scrub of DRAM is achieved every 
time the column address rolls over.

During scrub cycles, if the SWEN bit is cleared, the Falcon pair does not 
perform the write portion of the read-modify write cycle. If the SWEN bit 
is set, the Falcon pair does perform the write unless it encounters a double-
bit error during the read.

If so enabled, single- and double-bit scrub errors are logged, and the 
PowerPC 60x bus master is notified via interrupt.