Motorola MVME2300 Series 用户手册
Programming Model
http://www.motorola.com/computer/literature
3-31
3
Revision ID/ General Control Register
REVID
The REVID bits are hard-wired to indicate the revision
level of the Falcon. The values are $01 for the first
revision, $02 for the second.
level of the Falcon. The values are $01 for the first
revision, $02 for the second.
aonly_en
Normally, the Falcon pair responds to address-only cycles
only if they fall within the address range of one of its
enabled map decoders. When the aonly_en bit is set, the
Falcon pair also responds to address-only cycles that fall
outside of the range of its enabled map decoders provided
they are not acknowledged by some other slave within 8
clock periods. aonly_en is read-only and reflects the level
that was on the CKD4 pin at power-up reset.
only if they fall within the address range of one of its
enabled map decoders. When the aonly_en bit is set, the
Falcon pair also responds to address-only cycles that fall
outside of the range of its enabled map decoders provided
they are not acknowledged by some other slave within 8
clock periods. aonly_en is read-only and reflects the level
that was on the CKD4 pin at power-up reset.
isa_hole
When it is set, isa_hole disables any of the DRAM or
ROM/Flash blocks from responding to PowerPC accesses
in the range from $000A0000 to $000BFFFF. This has the
effect of creating a hole in the DRAM memory map for
accesses to ISA. When isa_hole is cleared, there is no hole
created in the memory map.
ROM/Flash blocks from responding to PowerPC accesses
in the range from $000A0000 to $000BFFFF. This has the
effect of creating a hole in the DRAM memory map for
accesses to ISA. When isa_hole is cleared, there is no hole
created in the memory map.
adis
When adis is clear, fast page mode operation is used for
back-to-back pipelined accesses to the same page within
DRAM. When it is set, RAS is cycled between accesses.
This bit should normally be cleared unless the Falcon has
a problem operating that way.
back-to-back pipelined accesses to the same page within
DRAM. When it is set, RAS is cycled between accesses.
This bit should normally be cleared unless the Falcon has
a problem operating that way.
Address
$FEF80008
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Name
REVID
0
0
0
0
0
0
ao
nl
nl
y_
en
en
isa
_
_
h
o
le
0
0
0
ad
is
is
ram
fre
f
ra
m
s
pd0
ra
m
s
pd1
ch
ip
ip
u
Operation
READ ZERO
READ ONLY
R
R
R
R
R
R
R
R/
W
W
R
R
R
R/
W
W
R/
W
W
R/
W
W
R/
W
W
R
Reset
X
X
X
X
X
X
X
X
V P
0 PL
X
X
X
0 P
1 P
0 P
0 P
V P