Motorola MVME2300 Series 用户手册
Functional Description
http://www.motorola.com/computer/literature
4-15
4
The Configuration Space enables are not the only things enabled after a
PCI reset. The LSI0 image may also not be disabled by a PCI reset,
regardless of the enable bit’s power-up condition. If the image is active at
the time the reset occurs, it will remain enabled through the reset.
Additionally, the image does not remain in the same VME or PCI address
range.
PCI reset. The LSI0 image may also not be disabled by a PCI reset,
regardless of the enable bit’s power-up condition. If the image is active at
the time the reset occurs, it will remain enabled through the reset.
Additionally, the image does not remain in the same VME or PCI address
range.
How many of the Power-Up (P/U) option bits actually get latched as the
Universe manual indicates they should, is uncertain. In any case, the EN
bit in the LSI0_CTL register is not latched; on MVME2300 series boards,
its P/U state is disabled but is not honored.
Universe manual indicates they should, is uncertain. In any case, the EN
bit in the LSI0_CTL register is not latched; on MVME2300 series boards,
its P/U state is disabled but is not honored.
Workarounds
The software cannot completely correct this problem, but can minimize the
effects of it. Two possible solutions are presented:
effects of it. Two possible solutions are presented:
Method 1
1. Modify the PCI probe code to disable each PCI device prior to
writing its configuration space BS registers. This will prevent the
Universe from being active on the PCI bus while it has a base
address of 0.
Universe from being active on the PCI bus while it has a base
address of 0.
2. Once the Universe has been assigned a valid PCI Base Address,
enable register space access and disable the LSI0 slave image by
clearing the EN bit of the LSI0_CTL register.
clearing the EN bit of the LSI0_CTL register.
Method 2
Modify the port 92 reset code to disable the LSI0 image before
propagating the reset. This will cause the LSI0 image to come up
disabled.
propagating the reset. This will cause the LSI0 image to come up
disabled.
MCG understands that both of these methods are awkward, because the
PCI probe/reset code should not contain any device-specific patches. It
should only need to follow the probing conventions of the PCI
specification. However, the only other option appears to be avoidance of
the LSI0 image altogether.
PCI probe/reset code should not contain any device-specific patches. It
should only need to follow the probing conventions of the PCI
specification. However, the only other option appears to be avoidance of
the LSI0 image altogether.
Tundra engineering describes the problem as follows: