Motorola MVME2300 Series 用户手册
1-8
Computer Group Literature Center Web Site
Board Description and Memory Maps
1
Default Processor Memory Map
After a reset, the Raven ASIC and the Falcon chip set provide the default
processor memory map as shown in the following table.
processor memory map as shown in the following table.
Notes
1. This default map for PCI/ISA I/O space allows software to
determine whether the system is MPC105-based or Falcon/Raven-
based by examining either the PIB Device ID or the CPU Type
register.
based by examining either the PIB Device ID or the CPU Type
register.
2. The first Megabyte of ROM/Flash bank A appears at this range after
a reset if the rom_b_rv control bit is cleared. If the rom_b_rv control
bit is set, then this address range maps to ROM/Flash bank B.
bit is set, then this address range maps to ROM/Flash bank B.
Table 1-2. Default Processor Memory Map
Processor Address
Size
Definition
No
te
te
s
Start
End
0000 0000
7FFF FFFF
2G
Not mapped
8000 0000
8001 FFFF
128K
PCI/ISA I/O Space
1
8002 0000
FEF7 FFFF
2G - 16M -
640K
Not mapped
FEF8 0000
FEF8 FFFF
64K
Falcon Registers
FEF9 0000
FEFE FFFF
384K
Not mapped
FEFF 0000
FEFF FFFF
64K
Raven Registers
FF00 0000
FFEF FFFF
15M
Not mapped
FFF0 0000
FFFF FFFF
1M
ROM/Flash Bank A or Bank B
2