Motorola MVME2300 Series 用户手册
1-24
Computer Group Literature Center Web Site
Board Description and Memory Maps
1
The register values in the table yield the following VMEbus slave map:
Falcon-Controlled System Registers
The Falcon chip set latches the states of the DRAM data lines onto the
PR_STAT1 and PR_STAT2 registers. MVME2300 series boards use these
status registers to provide the system configuration information. In
addition, the Falcon chip set performs the decode and control for an
external register port. This function is utilized by MVME2300 series
boards to provide the system control registers.
PR_STAT1 and PR_STAT2 registers. MVME2300 series boards use these
status registers to provide the system configuration information. In
addition, the Falcon chip set performs the decode and control for an
external register port. This function is utilized by MVME2300 series
boards to provide the system control registers.
The following subsections describe these system registers in detail.
Table 1-14. VMEbus Slave Map Example
VMEbus Address
Size
CHRP Map
PREP Map
Range
Mode
4000 0000 -
4000 0FFF
4000 0FFF
A32 U/S/P/D
D08/16/32
D08/16/32
4K
PCI/ISA I/O Space:
0000 1000 - 0000 1FFF
0000 1000 - 0000 1FFF
PCI/ISA I/O Space:
0000 1000 - 0000 1FFF
0000 1000 - 0000 1FFF
1000 0000 -
1FFF FFFF
1FFF FFFF
A32 U/S/P/D
D08/16/32/64
RMW
D08/16/32/64
RMW
256M
PCI/ISA Memory Space
(On-board DRAM)
0000 0000 - 0FFF FFFF
(On-board DRAM)
0000 0000 - 0FFF FFFF
PCI/ISA Memory Space
(On-board DRAM)
8000 0000 - 8FFF FFFF
(On-board DRAM)
8000 0000 - 8FFF FFFF
Table 1-15. System Register Summary
BIT # ---->
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
FEF80400
System Configuration Register (Upper Falcon’s PR_STAT1)
FEF80404
Memory Configuration Register (Lower Falcon’s PR_STAT1)
FEF88000
System External Cache
Control Register
FEF88300
CPU Control Register