Motorola MVME2300 Series 用户手册
Programming Model
http://www.motorola.com/computer/literature
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L2_PLL[0:3]
L2 Core Frequency to L2 Frequency divider. This field is
encoded as follows:
encoded as follows:
FLSHP[0:2]
Bank A Flash memory size. This field is encoded as
follows:
follows:
System External Cache Control Register (SXCCR)
The MVME2300 and MVME2300SC boards do not implement this
register. Writes to this register location ($FEF88000) will have no system
effects. Reads from this register location will return undefined data.
register. Writes to this register location ($FEF88000) will have no system
effects. Reads from this register location will return undefined data.
PLL Value]
Size
0B0000
Disable
0B0001
1
0B0010
1.5
0B0011
2
0B0100
2.5
0B0101
3
0B0110 to 0B1111
Reserved
Flash Size
FLSHP0_
FLSHP1_
FLSHP2_
1MB
0
0
0
2MB
0
0
1
4MB
0
1
0
8MB
0
1
1
16MB
1
0
0
32MB
1
0
1
64MB
1
1
0
No Flash
1
1
1