Motorola MVME2300 Series 用户手册
Functional Description
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2-21
2
Generating PCI Cycles
Four basic types of bus cycles can be generated on the PCI bus:
❏
Memory and I/O
❏
Configuration
❏
Special Cycle
❏
Interrupt Acknowledge
Generating PCI Memory and I/O Cycles
Each programmable slave may be configured to generate PCI I/O or
memory accesses through the MEM and IOM fields in its Attribute register
as shown below.
memory accesses through the MEM and IOM fields in its Attribute register
as shown below.
:
If the MEM bit is set, the Raven will perform Memory addressing on the
PCI bus. The Raven will take the MPC bus address, apply the offset
specified in the MSOFFx register, and map the result directly to the PCI
bus.
PCI bus. The Raven will take the MPC bus address, apply the offset
specified in the MSOFFx register, and map the result directly to the PCI
bus.
The IBM CHRP specification describes two approaches for handling PCI
I/O addressing: contiguous or spread address modes. When the MEM bit
is cleared, the IOM bit is used to select between these two modes whenever
a PCI I/O cycle is to be performed.
I/O addressing: contiguous or spread address modes. When the MEM bit
is cleared, the IOM bit is used to select between these two modes whenever
a PCI I/O cycle is to be performed.
The Raven will perform contiguous I/O addressing when the MEM bit is
clear and the IOM bit is clear. The Raven will take the MPC address, apply
the offset specified in the MSOFFx register, and map the result directly to
PCI.
clear and the IOM bit is clear. The Raven will take the MPC address, apply
the offset specified in the MSOFFx register, and map the result directly to
PCI.
MEM
IOM
PCI Cycle Type
1
x
Memory
0
0
Contiguous I/O
0
1
Spread I/O