Motorola MVME2300 Series 用户手册
2-28
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Raven PCI Bridge ASIC
2
With respect with the PCI bus, the RavenMPIC registers and the
configuration registers are always represented in little-endian mode.
configuration registers are always represented in little-endian mode.
The CONFIG_ADDRESS and CONFIG_DATA registers are actually
represented in PCI space to the processor and are subject to the endian
functions. For example, the powerup location of the CONFIG_ADDRESS
register with respect to the MPC bus is $80000CF8 when the Raven is in
big-endian mode. When the Raven is switched to little-endian mode, the
CONFIG_ADDRESS register with respect to the MPC bus is $80000CFC.
Note that in both cases the address generated internal to the processor will
be $80000CF8.
represented in PCI space to the processor and are subject to the endian
functions. For example, the powerup location of the CONFIG_ADDRESS
register with respect to the MPC bus is $80000CF8 when the Raven is in
big-endian mode. When the Raven is switched to little-endian mode, the
CONFIG_ADDRESS register with respect to the MPC bus is $80000CFC.
Note that in both cases the address generated internal to the processor will
be $80000CF8.
The contents of the CONFIG_ADDRESS register are not subject to the
endian function.
endian function.
The data associated with PIACK accesses is subject to the endian
swapping function. Because the address of a PIACK cycle is undefined,
address modification during little-endian mode is not an issue.
swapping function. Because the address of a PIACK cycle is undefined,
address modification during little-endian mode is not an issue.
Error Handling
The Raven is capable of detecting and reporting the following errors to one
or more MPC masters:
or more MPC masters:
❏
MPC address bus time-out
❏
PCI master signalled master abort
❏
PCI master received target abort
❏
PCI parity error
❏
PCI system error
Each of these error conditions will set an error status bit in the MPC Error
Status register. If a second error is detected while any of the error bits is
set, the OVFL bit is asserted, but none of the error bits are changed. You
can clear each bit in the MPC Error Status register by writing a 1 to it;
writing a 0 to it has no effect. New error bits may be set only when all
previous error bits have been cleared.
Status register. If a second error is detected while any of the error bits is
set, the OVFL bit is asserted, but none of the error bits are changed. You
can clear each bit in the MPC Error Status register by writing a 1 to it;
writing a 0 to it has no effect. New error bits may be set only when all
previous error bits have been cleared.